What is the reason for reset synchronization in new CL design template?

[za1nrkhan]

According to the AWS shell interface specification under Clocks and Reset:

The shell provides an active_low reset signal synchronous to clk_main_a0: rst_main_n. This is an active low reset signal, and is asserted while an AFI is being loaded. The reset signal is de-asserted after the AFI load is complete and the clocks are stable.

And yet there is this reset synchronization circuit present in the new CL template as well as in some of the example CL designs.

aws-fpga/hdk/common/shell_v04261818/new_cl_template/design/cl_template.sv

Lines 48 to 58 in 2a36c4d

	always_ff @(negedge rst_main_n or posedge clk)
	if (!rst_main_n)
	begin
	pre_sync_rst_n <= 0;
	sync_rst_n <= 0;
	end
	else
	begin
	pre_sync_rst_n <= 1;
	sync_rst_n <= pre_sync_rst_n;
	end

If the reset signal is synchronous to clk_main_a0, wouldn't it just make sense to connect rst_main_n directly in the design rather than passing it through the reset synchronization circuit?

[AWScsaralay]

Hello,

You are correct, although the reset synchronization is not absolutely required if using rst_main_n in the ``clk_main_a0``` domain. However, for ease of timing closure we strongly recommend pipelining the reset and reducing the global asynchronous resets in the design.

Of course, reset synchronization is required if rst_main_n is going to be used in other clock domains.

We hope that helps. Please let us know if you have any questions.

Thank you!
Chakra