Building DCP fails when using sh_ddr

[ChrisKjellqvist]

Using the master branch.
If I do not use the sh_ddr IP by setting DDR_A_PRESENT(0) for all of the DDR channels, then everything synthesizes without issue.

Whenever I do use the sh_ddr IP, it results in the following synthesis error:

INFO: [Synth 8-6157] synthesizing module 'lib_pipe' [/home/centos/aws-fpga/hdk/common/shell_v04261818/design/lib/lib_pipe.sv:27]
INFO: [Synth 8-6155] done synthesizing module 'lib_pipe' (63#1) [/home/centos/aws-fpga/hdk/common/shell_v04261818/design/lib/lib_pipe.sv:27]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/aws-fpga/hdk/common/shell_v04261818/design/sh_ddr/synth/sh_ddr.sv:606]
ERROR: [Synth 8-5809] Error generated from encrypted envelope. [/home/centos/aws-fpga/hdk/common/shell_v04261818/design/sh_ddr/synth/sh_ddr.sv:580]
ERROR: [Synth 8-6156] failed synthesizing module 'sh_ddr' [/home/centos/aws-fpga/hdk/common/shell_v04261818/design/sh_ddr/synth/sh_ddr.sv:32]
ERROR: [Synth 8-6156] failed synthesizing module 'composer_aws' [/home/centos/Composer/Composer-Hardware/vsim/design/composer_aws.sv:27]

Further up in the log is the following which may be related.

WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/src_register_slice/src_register_slice.xci
/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/dest_register_slice/dest_register_slice.xci
/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xci
/home/centos/aws-fpga/hdk/common/shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xci

Any help with this issue would be appreciated. Otherwise, I could generate another DDR controller IP using Vivado though the documentation seems to indicate that sh_ddr needs to be used in order for the toolchain to work correctly.

[AWScsaralay]

Hello,

Thanks for reaching out to us on this topic. Could you please help us answer following questions?

• Are you seeing this error when instantiating sh_ddr.sv and setting DDR_A_PRESENT=0? Or does it error out with DDR_A_PRESENT=1 too?
• Were you able to successfully build our example CL_DRAM_DMA design using the desired setting for sh_ddr.sv?
• Could you please confirm which tool version are you using?
• Were there any errors upon running source hdk_setup.sh? https://github.com/aws/aws-fpga/blob/master/hdk_setup.sh ?

Thank you!
Chakra

[ChrisKjellqvist]

Hi, I resolved the issue, but seemingly only by luck. I was initially setting up the repository using the prepare_new_cl.sh script. No errors were raised when DDR_<channel>_PRESENT=0 were set, only when these parameters were set to 1. I was compiling using the FPGA Development Images on AWS (Vivado 2021.1 if I remember correctly), and hdk_setup.sh ran without error.

Here was my solution, which, while unsophisticated, was frustrating to deal with. Within the provided synthesis tcl there are a pair of lines that are marked to be uncommented if using DDR. This is not sufficient to use DDR. I noticed within the synthesis script for the DDR example there are additional includes that are not listed within the provided template tcl, namely: mgt_acc_axl.sv and mgt_gen_axl.sv. Adding these to my synthesis tcl resolved the issue and sh_ddr synthesized without issue.

[ljp0101]

Just wasted time on this same and I second the @ChrisKjellqvist pull request.

The setup script doesn't work, and worse misleadingly implies it should work with DDR A/B/D if some commented code is uncommented (ignoring the obvious error about using read_bd on a .xcix). And nothing about what's required by the encrypted envelope is documented anywhere; we have to guess based off the examples.

[czfpga]

Hi,

Thank you for the feedback. I'll bring this to the dev team.

Chen