Inserting ILA is improving the performance
Gogul-N opened this issue · 4 comments
Hi,
Look at the above image. From module A, a gated clock is going to module B. We found that module B is not functioning properly. So, inserted ILA 1 in module B and found that gated clock is always high inside module B. To identify the root cause, we inserted ILA 2 in module A. After inserting the ILA 2 in module A, both modules are functioning as expected. And when we removed the ILA 2 in module A, again the same problem faced in module B.
What will be the cause of this issue?
NOTE: We are using BUFGMUX (to replace OR gate) for gated clock.
Thank you.
Hello!
Thank you for all the details, the issue appears to be a design issue. ILAs do not modify the functional behavior of the design. Have you been able to leverage the verification support provided in the aws-fpga developer kit to simulate and test your design before loading it on hardware?
A good place to get started would be RTL_Simulating_CL_Designs
Please feel free to reach out with any follow up questions!
Thanks,
-Joe
Hi @AWSjoeluc ,
Thank you for your reply.
While simulating the example design, I am getting the following errors.
ERROR: [USF-XSim-62] 'elaborate' step failed with error(s) while executing '/home/centos/src/project_data/aws-fpga/hdk/cl/examples/hello_world_hlx/example_projects/hello_world.sim/sim_1/behav/xsim/elaborate.sh' script. Please check that the file has the correct 'read/write/execute' permissions and the Tcl console output for any other possible errors or warnings.
ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
Thank you
Hi @Gogul-N,
- Does that file exist at the path in the message?
- Did you clone the repo and run all prior steps with the same user account?
- Can you try changing all the file permissions with
chmod -R ___ <top of hierarchy?
If nothing works, can you try a fresh clone and follow RTL_SIMULATING_CL_DESIGNS to run the simulation without any changes?
Thanks,
-Joe