Lumped RLC element support
nsluhrs opened this issue · 2 comments
Description: A clear and concise description of what the feature is.
Under Ansys HFSS I am able to assign a boundary condition on a 2d object which has it act like a lumped resistor inductor or capacitor, or some combination in parallel/series. Is this something that can be done in Palace? I am mostly interested in using this in the eigenmode simulation but other modes would be appreciated as well.
Add any other context or screenshots about the feature request here.
I am unsure of exactly how the mathematics underlying that boundary condition works but I know that when I assign the boundary in ansys I am required to supply a integration line along the direction of current flow. Is this something I could somehow adjust the surface impedance boundary condition to mimic or would it have to be a completely boundary setting?
Hi @nsluhrs, thanks for your question. What you are looking for is indeed already available in Palace using either the "Impedance" or "LumpedPort" boundaries, both of which are supported for time- and frequency-domain driven as well as eigenmode simulation types.
If all you want to do is prescribe a surface impedance on a 2D boundary, the "Impedance" boundary allows you to specify an arbitrary R, L, and C for a resistor, inductor, and capacitor which add in parallel. The mapping between the surface R/L/C quantities and the circuit ones is described here.
The "LumpedPort" boundary is probably closer to what HFSS offers. It's the same boundary condition as the "Impedance" boundary, but adds functionality for postprocessing things like lumped voltage/current across the port once you have the electric and magnetic field solutions. The same principle of an "integration line" is specified using the "Direction" keyword, which takes either a cartesian direction ("+X", for example), or a 3D vector specifying the voltage direction across the port (direction between conductors).
For further information, I recommend taking a look at:
- https://awslabs.github.io/palace/stable/guide/boundaries/#Impedance-boundary
- https://awslabs.github.io/palace/stable/config/boundaries/#boundaries[%22Impedance%22]
- https://awslabs.github.io/palace/stable/config/boundaries/#boundaries[%22LumpedPort%22]
- https://awslabs.github.io/palace/stable/examples/cpw/ (here we use lumped ports to excite a coplanar waveguide structure, these are equivalent to lumped resistor boundaries).
The reference section of the docs might also be useful.
Let me know if you have any further questions or if something is not working for you. Thanks for your interest!
@sebastiangrimberg , thank you for your quick and thorough response. I suspected the impedance boundary might be the right thing to use, but clearly did not read the documentation thoroughly enough.