babyworm's Stars
eine/hwd-ide
hdl/containers
Building and deploying container images for open source electronic design automation (EDA)
Nic30/hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
YosysHQ/yosys
Yosys Open SYnthesis Suite
AppFlowy-IO/AppFlowy
Bring projects, wikis, and teams together with AI. AppFlowy is an AI collaborative workspace where you achieve more without losing control of your data. The best open source alternative to Notion.
chipsalliance/omnixtend
OmniXtend cache coherence protocol
chipsalliance/Cores-SweRV-Support-Package
Processor support packages
pdfcpu/pdfcpu
A PDF processor written in Go.
pygments/pygments
Pygments is a generic syntax highlighter written in Python
rust-lang/chalk
An implementation and definition of the Rust trait system using a PROLOG-like logic solver
chipsalliance/VeeR-ISS
chipsalliance/Cores-VeeR-EH1
VeeR EH1 core
CertainLach/jrsonnet
Rust implementation of Jsonnet language
jklukas/memoir-sphinx
A sample project showing Sphinx output to the Latex Memoir class
jgraph/drawio
draw.io is a JavaScript, client-side editor for general diagramming.
specs-feup/specs-hw
Hardware-related libraries and applications
B-Lang-org/Documentation
Main page
B-Lang-org/bsc
Bluespec Compiler (BSC)
hyoukjun/OpenSMART
Public release
TigerVNC/tigervnc
High performance, multi-platform VNC client and server
dohyunkim/xetexko
typeset Korean with xe(la)tex
chipsalliance/sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
pulp-platform/bigpulp
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
lnis-uofu/OpenFPGA
An Open-source FPGA IP Generator
aignacio/ravenoc
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
olofk/fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
TencentARC/GFPGAN
GFPGAN aims at developing Practical Algorithms for Real-world Face Restoration.
openhwgroup/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
chipsalliance/firrtl
Flexible Intermediate Representation for RTL
IENT/YUView
The Free and Open Source Cross Platform YUV Viewer with an advanced analytics toolset