Pinned Repositories
Double-gate-Junctionless-transistor-silvaco-code-
JAMFET-VerilogA-LUT-models
learn-sky130
Learning to do things with the Skywater 130nm process
MIJAMFET-VerilogA-LUT-models
python-codes-for-semiconductor-
repository-of-basic-digital-circuit-building-blocks-in-verilog
this is a repository of basic digital building blocks used in RTL design. all blocks written in verilog and simulated in Xilinx vivado
ULJAMFET-VerilogA-LUT-models-
ULMIJAMFET-VerilogA-LUT-models-
Verilog-A-model-for-junctionless-transistor
JUNCTIONLESS TRANSISTOR VERILOG-A MODEL FOR CIRCUIT SIMULATION WITH GATE LENGTH OF 20nm
bashiryasir's Repositories
bashiryasir/MIJAMFET-VerilogA-LUT-models
bashiryasir/Double-gate-Junctionless-transistor-silvaco-code-
bashiryasir/JAMFET-VerilogA-LUT-models
bashiryasir/learn-sky130
Learning to do things with the Skywater 130nm process
bashiryasir/python-codes-for-semiconductor-
bashiryasir/repository-of-basic-digital-circuit-building-blocks-in-verilog
this is a repository of basic digital building blocks used in RTL design. all blocks written in verilog and simulated in Xilinx vivado
bashiryasir/ULJAMFET-VerilogA-LUT-models-
bashiryasir/ULMIJAMFET-VerilogA-LUT-models-
bashiryasir/Verilog-A-model-for-junctionless-transistor
JUNCTIONLESS TRANSISTOR VERILOG-A MODEL FOR CIRCUIT SIMULATION WITH GATE LENGTH OF 20nm