NSFPlay 2.5 roadmap

[bbbradsmith]

The following is a list of planned changes I want to finish before the stable release of 2.5:

• 5B emulation rewrite
  -- Tone/Envelope/Noise 0 = 1 (envelope is incorrect)
  -- Phase should increment and >= period. (Current implementation is weird.)
  -- MAME: https://github.com/mamedev/mame/blob/master/src/devices/sound/ay8910.cpp
  -- Amplifier model
  --- https://forums.nesdev.com/viewtopic.php?f=2&t=17745
  --- Hard knee amplification: https://github.com/bbbradsmith/nsfplay/compare/5b_amplifier
  -- 50% PVM of envelope by high frequency tone should work #43
• Loopy's new wave of FDS RE:
  -- https://forums.nesdev.com/viewtopic.php?p=232662#p232662
  -- Sweep test its lowpass filter
  -- Waveform DAC nonlinearity model? (Maybe just a slider from 0 perfect to 1 = big discontinuity... a harmonic recursion that remaps the ranges to 0-255 with overlap?)
  -- FDS verify all halts / non-halts
• OPL2 notes, may help VRC7 implementation: https://docs.google.com/document/d/18IGx18NQY_Q1PJVZ-bHywao9bhsDoAqoIn1rIm42nwo
• Onebus 2xAPU ?
• N163 what happens when you cut down a very long period with a short one (does it take multiple ticks to drop down phase? can probably read it back to test?)
• N163 take a close look at amplitude of multiplex vs non and see if it can be closer
  -- See: https://forums.nesdev.com/viewtopic.php?p=237121#p237121
• 2A03 volume curves
• 2A03 nonlinear volume, should standardize on square 15 = nonlinear version (for NSFe mixe compatibility)
  -- See: https://forums.nesdev.com/viewtopic.php?p=237121#p237121
• 2A03 verify all halts / non-halts (should be well documented by now, MMC5 should be same)
• N163 verify all halts / non-halts
• VRC6 verify all halts / non-halts
• 5B / VRC7 halts should be known now
• Conflict between $E000 silence of N163/VRC7 with 5B multichip? (Block these in multichip. Only N163 actually implements it currently.)
• VRC7 test register, VRC7 $E000 register.
• APU square period should be 8 not 16 long and instead internal period register should be doubled to simulate 1/2 clock divider.
• Triangle "silence on 0" seems to reveal inconsistent halting behaviour, may also affect init option? (Does triangle init explicitly init to phase 0 correctly?)
• Test CPU again.
• OPLL + VRC7 as TNS cart See: #54

[bbbradsmith]

Moving this stuff to the 3.0 roadmap instead. A lot of it would be easier to do in 3.0.