Segmentation Fault while executing ABC

[Usmankiani-rs]

Hello

I am trying to generate netlist using DTI 16 nm library through Yosys.

Steps for generating netlist:
read_verilog xxx.v
synth -top top_module_name
dfflibmap -liberty dti_lib_file
abc -liberty dti_lib_file
opt -fast
write_verilog netlist.v

I am facing segmentation fault while executing abc command.

After debugging my conclusions are size of information in DTI library is very large (approx 109 Million lines) which Yosys/abc can't handle.

How I come to the above conclusion?

Successfully generated netlist using sky water 130nm and TSMC 16nm. (Information size of these two libs are very small compared to DTI thats why Yosys/abc was able to generate netlist.)
Did another test case: trim down DTI lib to the size of TSMC lib. (Yosys was able to generate netlist but I have removed a large number of cells and their related info.)

My goal is to generate the netlist of complicated rtls of SoC blocks using DTI 16nm.

Now it is extremely difficult for me to trim down the lib file every time when I want to generate netlist of any complicated RTLs. (As I don't know which cells I have to remove or are required for mapping specific rtl logic)

Can you please give me an alternative solution as I don't want to change/remove any thing from DTI provided Lib file.

Thanks

Expected Behavior
Tool should be able to generate the netlist using DTI 16 nm lib (Doesn't matter whats the size of lib file)

Actual Behavior
ABC is spitting out segmentation fault.

[Usmankiani-rs]

resolved in latest release