berkeley-abc/abc

Issues

• How to determine the mapping between input/output variables in my .blif or pla file and the variables created for a CNF?

  #243 opened a year ago
  0

• command:print_delay

  #238 opened a year ago
  0

• Is there any book to teach how to use abc

  #237 opened a year ago
  1

• ABC preformance when read_lut

  #235 opened a year ago
  0

• Where's the hidden command

  #234 opened a year ago
  0

• How to use command `%pdra`

  #233 opened a year ago
  0

• ABC mapping worse in recent version

  #229 opened 2 years ago
  2

• Question about the software

  #227 opened 2 years ago
  0

• LUTs not topologically sorted after write_verilog

  #222 opened 2 years ago
  0

• bug: cone sometimes complements the output + Workaround

  #221 opened 2 years ago
  0

• Question: abc's solver configuration for HWMCC'20?

  #216 opened 2 years ago
  6

• `read_truth` with a binary input cannot create constant functions, but hex inputs can?

  #214 opened 2 years ago
  3

• ABC assumes `read_truth` value is hexadecimal, but examples use binary

  #213 opened 2 years ago
  0

• Can we read mockturtle::aig_network object with ABC?

  #212 opened 2 years ago
  1

• Question: generate sub-miters / partition the miter

  #211 opened 2 years ago
  5

• How can I check liveness property in aiger by ABC?

  #210 opened 2 years ago
  0

• 1

  #209 opened 2 years ago
  0

• Some ABC9 commands can not run!!!!

  #208 opened 2 years ago
  3

• Segfault during retiming due to insufficient alloc

  #207 opened a year ago
  0

• identifier "ABC_PTRINT_T" is undefined

  #205 opened 2 years ago
  0

• Output of ABC Command Execution Buffer

  #204 opened 2 years ago
  0

• Suppress Warning messages from ABC

  #203 opened 2 years ago
  1

• Assertion error while running resub: Assertion `Vec_PtrSize(pMan->vStackReplaceOld) == 0' failed.

  #202 opened 2 years ago
  0

• Does the programmable cell description of dsd_match include NOT?

  #201 opened 2 years ago
  0

• Abc generates verilog which can't be directly passed to downstreaming physical design flow

  #200 opened 2 years ago
  1

• Does the saucy code carry a noncommercial-only license?

  #198 opened 2 years ago
  0

• abc gen command

  #192 opened 2 years ago
  0

• Is it support multi-thread

  #191 opened 2 years ago
  0

• Feature request: mapping between latch and variables in CNF

  #190 opened 2 years ago
  0

• Error: Abc_CommandAbc9Strash(): There is no AIG

  #189 opened 2 years ago
  3

• Feature request: emit comprehensible error message instead of just asserting

  #188 opened 2 years ago
  4

• never mind

  #186 opened 2 years ago
  0

• Is XAIG &rewrite implemented?

  #184 opened 2 years ago
  0

• amap can't get the minimum area

  #182 opened 2 years ago
  0

• abc fails to read bluespec generated verilog

  #181 opened 2 years ago
  1

• Disabling usage of readline header when only C++ API to avoid depending on libreadline-dev package

  #174 opened 3 years ago
  1

• write_blif, write_pla

  #172 opened 3 years ago
  1

• A pdr performance issue？

  #171 opened 3 years ago
  3

• Is there a command for printting the information about lut mapping?

  #170 opened 3 years ago
  0

• show command

  #169 opened 3 years ago
  1

• Source code manual

  #168 opened 3 years ago
  0

• SOP print

  #167 opened 3 years ago
  2

• Espresso

  #166 opened 3 years ago
  2

• Encountering If_ObjPerformMappingChoice: Assertion `pCutSet->nCuts > 0' failed.

  #165 opened 3 years ago
  2

• Logic circuit generation from ABC Tool

  #164 opened 3 years ago
  0

• Regarding MIG

  #163 opened 3 years ago
  1

• blif file for full adder

  #162 opened 3 years ago
  1

• Supergate matching to k-feasible cuts in standard cell mapping

  #161 opened 3 years ago
  0

• Error in function ‘Abc_CommandMuxStruct’

  #155 opened 3 years ago
  0

• MinGW-w64–compiled `abc` segfaults when run in directory with at least one `.exe` file

  #154 opened 3 years ago
  3