bidoy

bidoy's Stars

• chipsalliance/chisel-template

  A template project for beginning new Chisel work

  Language:Scala628189

• rsnikhil/RISCV_Piccolo_v1

  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).

  Language:Verilog336

• f32c/f32c

  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz

  Language:C413105

• cnrv/riscv-soc-book

  关于RISC-V你所需要知道的一切

  55367

• seldridge/rocket-rocc-examples

  Tests for example Rocket Custom Coprocessors

  Language:C7327

• YosysHQ/picorv32

  PicoRV32 - A Size-Optimized RISC-V CPU

  Language:Verilog3.4k805

• riscv/riscv-debug-spec

  Working Draft of the RISC-V Debug Specification Standard

  Language:Python47996

• chipsalliance/riscv-dv

  Random instruction generator for RISC-V processor verification

  Language:Python1.1k336

• mdsalman729/flexpret_project

  Validating real time multithreaded applications on the flexpret architecture

  Language:C++11

• freecores/bluespec-h264

  Bluespec H.264 Decoder

  Language:Bluespec115

• bluespec/Piccolo

  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

  Language:Verilog32150

• westerndigitalcorporation/swerv_eh1

  A directory of Western Digital’s RISC-V SweRV Cores

  Language:SystemVerilog863132

• chenzhi1992/TensorRT-SSD

  Use TensorRT API to implement Caffe-SSD， SSD（channel pruning）， Mobilenet-SSD

  Language:C++25084