bingoshu

4096bit-IDDMM-Verilog

4096bit Iterative digit-digit Montgomery Multiplication in Verilog

AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

AD

Altium Desinger

AhaM3SoC

SoC Based on ARM Cortex-M3

AHB2

AMBA AHB 2.0 VIP in SystemVerilog UVM

AHB_Bus_Matrix

amba3-vip

amba3 apb/axi vip

antikernel-ipcores

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

ARM9-compatible-soft-CPU-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

ARM_documents

Documents for ARM

bingoshu/AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

bingoshu/AHB2

AMBA AHB 2.0 VIP in SystemVerilog UVM

bingoshu/async_mem_example

Construct async read memory from block memory in FPGA

bingoshu/basic_cache_core

bingoshu/Cache-Controller

Cache controller based on verilog with cache coherence for two processors

bingoshu/ComputerArchitectureLab

This repository is used to release the Labs of Computer Architecture Course from USTC

bingoshu/CoPHEE

CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.

bingoshu/cryptech

Collection of CrypTech repos to making cloning easier.

bingoshu/Guide-to-FPGA-Implementation-of-Arithmetic-Functions

Examples from the book by Deschamps et al. https://www.amazon.com/Implementation-Arithmetic-Functions-Electrical-Engineering/dp/9400729863

bingoshu/H264

H264视频解码verilog实现

bingoshu/HuffmanCode

hardware implement of huffman coding(written in verilog)

bingoshu/lisnoc

LIS Network-on-Chip Implementation

bingoshu/Modular_exponentiation_in_VHDL

Modular exponentiation in VHDL with Montgomery's multiplication enhanced with Karatsuba's algorithm.

bingoshu/montgomery_hw

KU Leuven DDP - Montgomery hardware project Group 12

bingoshu/MontgomeryDDP

bingoshu/OFDM-baseband

Verilog实现OFDM基带

bingoshu/Peppa-Pig

使用python turtle库画一只小猪佩奇

bingoshu/qdi-sdm-noc

A QDI spatial division multiplexing (SDM) NoC

bingoshu/RSA

A Montgomery modular multiplication block for a RSA module

bingoshu/RSA4096

4096bit RSA project, with verilog code, python test code, etc

bingoshu/security_stack

Set of security modules interfaced on the AXI4 bus

bingoshu/sha256_multicores

a sha256 hardware design with 4 lines of pipelines and use 4 cores to accelerate calculation

bingoshu/simple_SoC

Small and simple, primitive SoC with GPU, CPU, RAM, GPIO

bingoshu/SM4-SBOX

Verilog Implementation of SM4 s-box

bingoshu/Softmax_CNN

This repository contains full code of Softmax Layer in Verilog

bingoshu/stx_cookbook

Altera Advanced Synthesis Cookbook 11.0

bingoshu/tnoc

Network on Chip Implementation written in SytemVerilog

bingoshu/turbo-interleaver

两级流水线的LTE4路并行输出的turbo码交织器

bingoshu/turtle

使用python的turtle画樱花树，玫瑰，圣诞树，小猪佩奇，蛋糕，小黄人，贪吃蛇游戏61行代码

bingoshu/vdf-fpga

A low latency modulo squaring algorithm using Montgomery multiplication, submitted to the VDF FPGA design competition, targeting AWS FPGAs. Was awarded first prize for lowest latency in alternative approaches category.