Thin margin in blocks of circuit plots
Opened this issue · 2 comments
Current plotting mechanism consists in drawing small blocks (1 block ⁄ qubit ⨉ moment) and then joining them together.
It seems like circuit plots drawn by joining blocks have a visual artifact: a small margin around the blocks. For example, check the image in #18.
It is unknown if this is an artifact of our code or a bug in Luxor.jl
I think this is the intended behavior of svg images. Since we draw each of these cells one by one, the visualization of svg images in VSCode shows a small separation, but if we download the file and we open it with a program that supports vectorized images (e.g. Inkscape) we can clearly see that this separation does not exist:
Furthermore, if we take this same image in VSCode and we zoom in, we can also see how the separation vanishes:
To conclude, I would say that the drawing is fine and this is an artifact of the visualization in VSCode. However, if we wanted to fix this problem we would have to first draw the background of the whole canvas, and then draw the circuit elements on top of that, I could try to do this.
To conclude, I would say that the drawing is fine and this is an artifact of the visualization in VSCode. However, if we wanted to fix this problem we would have to first draw the background of the whole canvas, and then draw the circuit elements on top of that, I could try to do this.
It make sense that the artifact is the fault of the VSCode renderer but I don't completely agree with the solution because the separation margin appears also between wires.
The solution would be to draw the full lines instead of drawing the cells and joining. This also would make the rendering somewhat less complex as it would involve less SVG elements. However, the code would need to be a lil more complex.