This repo holds the Gem5 source code for the following works on multi-core Real-time cache coherence mechanisms
- A Systematic Approach to Achieving Tight Worst-Case Latency and High-Performance Under Predictable Cache Coherence at RTAS 2021
- Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems at IEEE Transactions on Computers 20202
- CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems at RTSS 2019
- Automatic Construction of Predictable and High-Performance Cache Coherence Protocols for Multi-Core Real-Time Systems IEEE Transactions on Computer Aided Design 2021
- CARP - Mixed criticality snooping bus-based cache coherence protocol (RTSS 2019)
- MSI - Conventional snooping bus-based MSI protocol
- PMSI - Predictable snopping bus-based MSI protocol (IEEE TC 2020)
- MESI - Conventinoal snooping bus-based MESI protocol
- PMESI - Predictable snooping bus-based MESI protocol (IEEE TC 2020)
- PMSI_C2C - PMSI with cache-to-cache transfers (RTAS 2021)
- PMESI_C2C - PMESI with cache-to-cache transfers (RTAS 2021)
- MOESI - Conventional snooping bus-based MOESI protocol
- PMOESI - Predictable snooping bus-based MOESI protocol
- MESIF - Conventional snooping bus-based MESIF protocol (IEEE TCAD 2021)
- PMESIF - Predictable snooping bus-based MESIF protocol (IEEE TCAD 2021)
- LPMI - Linear predictable snooping bus-based MI protocol (RTAS 2021)
- LPMSI - Linear PMSI (RTAS 2021)
- LPMESI - Linear PMESI (RTAS 2021)
- LPMOESI - Linear PMOESI (RTAS 2021)
- The build-all.sh script will build all the above flavors of the real-time cache coherence protocols for different core counts (2, 4, and 8 cores)
src/cpu/testers/rubytest/Trace.hhcontrols several parameters of the real-time arbitration policy. One can control the arbitration schedule, the allocation of time slots to cores for mixed-criticality scheduling, and the type of arbitration policy (round-robin, TDM, slack slot scheduling).
For any questions, please contact Anirudh Kaushik at amkaushi@uwaterloo.ca