Generate Verilog / VHDL code for fixpoint filters using jinja templates
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chipmuenk commented
This is not to replace Amaranth HDL generation but rather to complement it, e.g. for easy reverse engineering and parametrization of legacy Verilog / VHDL code
https://www.ericmacedo.com/generating-code-from-templates-using-python-and-jinja2.html