Issues
- 4
Do you have a plan to support SweRV-EL2 ?
#28 opened by kidonglee - 1
- 6
- 0
- 21
bscan_tap module - how does it work?
#29 opened by agrobman - 1
rvfpga on Nexys video: Error: Timed out after 1s waiting for sbbusy to go low
#66 opened by AmirhosseinR - 2
- 7
axi/wb bus cycle times
#55 opened by jamesbbecker - 1
fusesoc run --target=arty_a7 swervolf
#57 opened by nimra471 - 1
SweRV EL2 with External Sram memory issue
#60 opened by nimra471 - 1
simple_spi.v file not found in the repository
#56 opened by Sesib - 3
Error when building Zephyr example
#63 opened by aleksaj-vtool - 2
Error with "Build Zephyr applications"
#24 opened by kidonglee - 1
Unable to run Simulation using FuseSoC
#62 opened by vignajeth - 1
Compilation Errors while running SweRVolf
#61 opened by vignajeth - 2
- 1
Zephyr with adxl362 fails to compile
#14 opened by ddandare - 0
Tested/Implemented on other cores
#58 opened by geoalx - 3
Setup fails with error about cdc_utils
#54 opened by paulcobb27 - 0
- 5
- 0
Linux Compatibility
#50 opened by SOUMYADIPSAHA10 - 1
Linux compatibility
#49 opened by JOHNTBIJU - 1
- 2
how to change the CPUs clock frequency
#47 opened by kuoyaoming93 - 3
- 4
Running Compliance Test for Swerv
#44 opened by YeuzhiHere - 0
ERROR: [Labtools 27-3165] End of startup status: LOW when [ run --target=nexys_a7 --flag=cpu_el2 swervolf]
#43 opened by nicolast0604 - 2
- 2
- 1
Do you have any plan to support SweRV-EH2.
#37 opened by nicolast0604 - 0
- 1
Fusesoc Simulation Error
#31 opened by mhamzaali - 1
Boot Switches table error
#35 opened by ddandare - 6
Unsupported board in build Zephyr applications
#21 opened by cst-kirank - 2
VERSION_PATCH macro not defined
#16 opened by luispimo - 2
openocd timeout occurs when trying to load elf file using command 'load_image'.
#42 opened by nikhill-agnisys - 12
fusesoc build and run using xcelium
#41 opened by nikhill-agnisys - 2
LItedram Generation
#36 opened by lindajames101 - 8
- 19
- 0
Swerv configuration & Swervolf
#30 opened by agrobman - 12
debugging is not working !!!
#26 opened by kidonglee - 0
verilator + openocd + gdb simulation issue
#25 opened by kidonglee - 4
build w/ fusesoc run --target=sim swervolf fails when generating swervolf-intercon:0.7
#15 opened by profroyk - 2
Running pre-compiled zephyr examples failed
#20 opened by cst-kirank - 1
Adding a new target, configuring the el2 core
#18 opened by altuSemi - 1
SImulation run error
#17 opened by altuSemi - 2
Riviera-PRO common compilation
#12 opened by dawidzim - 1
Compilation failed for EH1 with Verilator
#11 opened by tunghoang290780