chipsalliance/VeeRwolf

verilator + openocd + gdb simulation issue

kidonglee opened this issue · 0 comments

I have some problem when running simulation with "verilator+openocd+gdb".
'step' or 'continue' command in gdb do not work well. (there is no next gdb prompt after the commands)
I don't know what the problem is.
Please help me.

Actually, I run the test as below,
- run simulation in terminal A
fusesoc run --target=sim swervolf --jtag_vpi_enable
- run openocd in terminal B
openocd -f $SWERVOLF_ROOT/data/swervolf_sim.cfg
- run gdb in terminal C (hello.elf is build in sw folder)
riscv64-unknown-elf-gdb ./hello.elf
- gdb commands
(gdb) set remotetimeout 50000
(gdb) target remote localhost:3333
(gdb) load
(gdb) s
--> no response forever

Thank you.