LItedram Generation
lindajames101 opened this issue · 3 comments
lindajames101 commented
Did you generate Litedram with axi signals or you later added axi signals yourself after generating v files? If we generate litedram from enjoy-digital/litedram, there are no axi signals by default.
Regards
Linda
olofk commented
Hi Linda,
For SweRVolf I have used this configuration file for LiteDRAM
# This file is Copyright (c) 2018-2019 Florent Kermarrec <florent@enjoy-digital.fr>
# License: BSD
{
# General ------------------------------------------------------------------
"cpu": "serv", # Type of CPU used for init/calib (vexriscv, lm32)
"speedgrade": -1, # FPGA speedgrade
"memtype": "DDR2", # DRAM type
# PHY ----------------------------------------------------------------------
"cmd_delay": 0, # Command additional delay (in taps)
"cmd_latency": 0, # Command additional latency
"sdram_module": "MT47H64M16", # SDRAM modules of the board or SO-DIMM
"sdram_module_nb": 2, # Number of byte groups
"sdram_rank_nb": 1, # Number of ranks
"sdram_phy": "A7DDRPHY", # Type of FPGA PHY
# Frequency ----------------------------------------------------------------
"input_clk_freq": 100e6, # Input clock frequency
"sys_clk_freq": 100e6, # System clock frequency (DDR_clk = 4 x sys_clk)
"iodelay_clk_freq": 200e6, # IODELAYs reference clock frequency
# Core ---------------------------------------------------------------------
"cmd_buffer_depth": 16, # Depth of the command buffer
# User Ports ---------------------------------------------------------------
"user_ports": {
"axi_0" : {
"type": "axi",
"id_width": 6,
},
},
# CSR Port -----------------------------------------------------------------
"csr_expose": "False", # Expose CSR bus as I/Os
"csr_align" : 32, # CSR alignment
}
I will try to get this into the repository together with instructions for how to regenerate the LiteDRAM core
lindajames101 commented
Thanks A lot