fusesoc build and run using xcelium
nikhill-agnisys opened this issue · 12 comments
Hello,
I have successfully able to run this environment using verilator. However when I try to simulate this flow using 'xcelium', I get below error from makefile.
My command line is "fusesoc run --target=sim --tool=xcelium swervolf".
In case I am missing something, please let me know.
Thanks and Regards,
Nikhil Arora
Hello,
I am facing issue while running xcelium simulation
return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1;
|
xmelab: *E,CFNOSF (../src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv,58|50): System function calls are not allowed in constant functions [10.3.5(IEEE)].
parameter int unsigned IdxWidth = cf_math_pkg::idx_width(NoIndices),
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xmelab: *N,CFCALL (../src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv,53|58): Function cf_math_pkg::idx_width treated as a constant function because of this call.
Looking at the first error it seems like it can't find xcelium. I'm not a xcelium user myself but could it be that xmroot is pointing to the wrong directory.
Not sure about what to do with the issues in common_cells. Any clues @zarubaf? I saw something related to idx_width in the common_cells changelog. Perhaps we need to bump the depdenency on common_cells to a newer version?
Uff, my friend xcelium. I think the tool might have problems with the $clog in the function. I remember us using the very same function in xcelium though, so I wonder whether this is something that might have been fixed in a newer version :/
Offending code:
https://github.com/pulp-platform/common_cells/blob/29a88adfce24e242162138522c25993a89e2b539/src/cf_math_pkg.sv#L58
new version of sv files or the xcelium version.
Xcelium
Thanks, i will check if i am using latest version.
And with questa simulation i am getting these errors
do edalize_main.tcl
** Error (suppressible): (vlog-1902) Option "-svinputport=compat" is either unknown, requires an argument, or was given with a bad argument.
Use the -help option for complete vlog usage.
** Error: /auto/cae/mentor/questa_10.5_ams/questasim/v10.5/linux_x86_64/vlog failed.
Executing ONERROR command at macro ./edalize_build_rtl.tcl line 2
make: *** [Makefile:42: work] Error 1
ERROR: Failed to build ::swervolf:0.7.3 : '['make']' exited with an error: 2
Thanks, i will check if i am using latest version.
And with questa simulation i am getting these errors
do edalize_main.tcl
** Error (suppressible): (vlog-1902) Option "-svinputport=compat" is either unknown, requires an argument, or was given with a bad argument.
Use the -help option for complete vlog usage.
** Error: /auto/cae/mentor/questa_10.5_ams/questasim/v10.5/linux_x86_64/vlog failed.
Executing ONERROR command at macro ./edalize_build_rtl.tcl line 2
make: *** [Makefile:42: work] Error 1
ERROR: Failed to build ::swervolf:0.7.3 : '['make']' exited with an error: 2
After updating the questa sim to latest version these error was fixed but after that I was getting some macro missing error in the RTL For which added the "config/common_defines.vh" in "build/swervolf_0.7.3/sim-modelsim/edalize_build_rtl.tcl".
And had to run make file directly in "build/swervolf_0.7.3/sim-modelsim" directory instead of running fusesoc command
after the above process now i am getting this error:
** Note: (vsim-3812) Design is being optimized...
** Fatal: Unexpected signal: 11.
../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/swerv.sv(1317): Vopt Compiler exiting
** Error: (vopt-2064) Compiler back-end code generation process terminated with code 211.
Error loading design
Error loading design
Any Idea to fix this issue??
return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1; |xmelab: *E,CFNOSF (../src/pulp-platform.org__common_cells_1.20.0/src/cf_math_pkg.sv,58|50): System function calls are not allowed in constant functions [10.3.5(IEEE)].
parameter int unsigned IdxWidth = cf_math_pkg::idx_width(NoIndices),
|
xmelab: *N,CFCALL (../src/pulp-platform.org__common_cells_1.20.0/src/addr_decode.sv,53|58): Function cf_math_pkg::idx_width treated as a constant function because of this call.
These errors were fixed after installing latest version but after that I was getting follwoing errors:
xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,217|23): AXI_TYPEDEF_AW_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)]. AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t)
|
xmvlog: *E,EXPENM (../src/swervolf-intercon_0.7.3/axi_intercon.v,217|24): expecting the keyword 'endmodule' [12.1(IEEE)].
AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,218|23): AXI_TYPEDEF_AW_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,219|22): AXI_TYPEDEF_W_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,220|22): AXI_TYPEDEF_B_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,221|22): AXI_TYPEDEF_B_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,223|23): AXI_TYPEDEF_AR_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t)
To solve the above i added the "config/common_defines.vh" in "build/swervolf_0.7.3/sim-xcelium/edalize_build_rtl.f" and run the simulation directly with make command instead of "fusesoc" and it worked with this process.
These errors were fixed after installing latest version but after that I was getting follwoing errors:
xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,217|23):
AXI_TYPEDEF_AW_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].AXI_TYPEDEF_AW_CHAN_T(aw_chan_mst_t, addr_t, id_mst_t, user_t)
|
xmvlog: *E,EXPENM (../src/swervolf-intercon_0.7.3/axi_intercon.v,217|24): expecting the keyword 'endmodule' [12.1(IEEE)].
AXI_TYPEDEF_AW_CHAN_T(aw_chan_slv_t, addr_t, id_slv_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,218|23):AXI_TYPEDEF_AW_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_W_CHAN_T(w_chan_t, data_t, strb_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,219|22):AXI_TYPEDEF_W_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_B_CHAN_T(b_chan_mst_t, id_mst_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,220|22):AXI_TYPEDEF_B_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_B_CHAN_T(b_chan_slv_t, id_slv_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,221|22):AXI_TYPEDEF_B_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
AXI_TYPEDEF_AR_CHAN_T(ar_chan_mst_t, addr_t, id_mst_t, user_t) | xmvlog: *E,NOTDIR (../src/swervolf-intercon_0.7.3/axi_intercon.v,223|23):AXI_TYPEDEF_AR_CHAN_T: not a recognized directive or macro [2.7.3][16.3.1][16(IEEE)].
`AXI_TYPEDEF_AR_CHAN_T(ar_chan_slv_t, addr_t, id_slv_t, user_t)To solve the above i added the "config/common_defines.vh" in "build/swervolf_0.7.3/sim-xcelium/edalize_build_rtl.f" and run the simulation directly with make command instead of "fusesoc" and it worked with this process.
In my experience that can be caused by an actual RTL bug, if the source file forgot to include the include file. Different simulators have a different take on what has been included and is visible by other files. I am not totally in the picture of axi_intercon but if this is auto-generated you might need to adapt the script/template.
I had similar problems with Questa and VCS previously.
Yes I faced the same issue with questa sim but solved by same process by editing the file build/swervolf_0.7.3/sim-modelsim/edalize_build_rtl.tcl
Possibly, in initial build the files ".f" for xcelium and ".tcl" fo questa is not generating properly with fusesoc command