how to change the CPUs clock frequency

[kuoyaoming93]

Hi @olofk,

I'm trying to add new features/operations and make experiments with the SweRV-EL2 core.
So I would like to be able to change the clock frequency and make it independent from the DDR controller / AXI CDC.

I saw the clock diagram here, but I don't know where to touch in order to change only the clk_core since this signal is related to AXI cdc. When I try to modify frequency of clk_core, I have timing issues there.

Thanks in advance,
Yao-Ming

[olofk]

Hi @kuoyaoming93,

It is possible to change core_clk independent of the DDR interface. I did that a lot when I was experimenting to see how fast I could run EH1 and EL2. You will need to make changes in this file https://github.com/chipsalliance/Cores-SweRVolf/blob/master/rtl/clk_gen_nexys.v if you're using the Nexys A7 board. There's a similar one for Basys3 as well. The basic formula is 100MHz*CLKFBOUT_MULT/CLKOUT0_DIVIDE/DIVCLK_DIVIDE but there are some other rules you must follow. Check the Xilinx datasheets for those.

Or perhaps you already found those? In that case, what changes did you make? Be aware that EL2 can't run much faster than 25MHz on these Xilinx FPGAs

[kuoyaoming93]

Thank you for your quick response Olof, and sorry for the delay.
I'm using the Nexys A7 board. The first time I also modified the clk_gen_nexys.v flie and got timing issues. I rebuilt the SoC again and everything is fine now. My bad.

Thank you again,
Yao-Ming