chnjstyj

Pinned Repositories

cache
cpu的cache和cache控制器
Language:Verilog30
asm
Language:Assembly00
chisel-resource-code
Language:Scala00
chisel-template
Language:Scala00
chnjstyj.github.io
Language:HTML00
cpu_with_cache
Language:Verilog00
fpga
fpga通用代码
00
mips-cpu
MIPS CPU implemented in Verilog
Language:Verilog00
nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
Language:SystemVerilog00
nscscc-mips-cpu
Language:Verilog00

chnjstyj's Repositories

chnjstyj/ysyx_exam
Language:C
chnjstyj/switcher_simulator
Language:C++
chnjstyj/chisel-template
Language:Scala
chnjstyj/SteamServerFilter
Language:C#
chnjstyj/cache
cpu的cache和cache控制器
Language:Verilog3
chnjstyj/source-server-query
Language:C#
chnjstyj/chisel-resource-code
Language:Scala
chnjstyj/cpu_with_cache
Language:Verilog
chnjstyj/nscscc-mips-cpu
Language:Verilog
chnjstyj/chnjstyj.github.io
Language:HTML
chnjstyj/fpga
fpga通用代码
chnjstyj/nscscc-wiki
NSCSCC 信息整合
chnjstyj/SHIT-Core-NSCSCC2020
a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
chnjstyj/nontrivial-mips
NonTrivial-MIPS is a synthesizable superscalar MIPS processor with branch prediction and FPU support, and it is capable of booting linux.
chnjstyj/asm
Language:Assembly
chnjstyj/zipcpu
A small, light weight, RISC CPU soft core
chnjstyj/nscscc2019ucas
chnjstyj/Sirius
Asymmetric dual issue in-order microprocessor.
chnjstyj/qspiflash
A set of Wishbone Controlled SPI Flash Controllers
chnjstyj/Uranus
Uranus MIPS processor by MaxXing & USTB NSCSCC team
chnjstyj/mips-cpu
MIPS CPU implemented in Verilog