HelloThemisto fails to compile with Vivado 2020.2

[zrlhle]

Running ./sra build pr completes with the following error:

[hle .../cloudFPGA/cFp_HelloThemisto]$ ./sra build pr
[sra:INFO] Starting to to build a partial reconfiguration design for role msg-ring-app...
./cFDK/SRA/LIB/bash/assert_envs.sh
make -C /ibm/gpfs-dataP/hle/cloudFPGA/cFp_HelloThemisto/ROLE/1
make[1]: Entering directory `~/cloudFPGA/cFp_HelloThemisto/ROLE/1'
make[2]: Entering directory `~/cloudFPGA/cFp_HelloThemisto/ROLE/1/hls'
make[3]: Entering directory `~/cloudFPGA/cFp_HelloThemisto/ROLE/1/hls/triangle_app'
make[3]: Nothing to be done for `all'.
make[3]: Leaving directory `~/cloudFPGA/cFp_HelloThemisto/ROLE/1/hls/triangle_app'
make[2]: Leaving directory `~/cloudFPGA/cFp_HelloThemisto/ROLE/1/hls'
-- Creating ip/ip_user_files directory -----------
mkdir -p ip/ip_user_files
cd ./tcl/ ; vivado -mode batch -source create_ip_cores.tcl -notrace -log create_ip_cores.log 

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source create_ip_cores.tcl -notrace
<cloudFPGA> ################################################################################
<cloudFPGA> ##
<cloudFPGA> ##  CREATING IP CORES FOR THIS ROLE 
<cloudFPGA> ##
<cloudFPGA> ################################################################################
<cloudFPGA> Start at: 20:09:17 Sat Jan 22 2022 

<cloudFPGA> The managed IP directory already exists. 
<cloudFPGA> <D1> Done with the cleaning of: '~/cloudFPGA/cFp_HelloThemisto/ROLE/1/ip/ip_user_files' 
<cloudFPGA> Creating the managed IP project directory: '~/cloudFPGA/cFp_HelloThemisto/ROLE/1/ip/managed_ip_project' 
<cloudFPGA> Creating the managed IP project: 'managed_ip_project.xpr' 
<cloudFPGA> 
<cloudFPGA> 
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository '~/cloudFPGA/cFp_HelloThemisto/ROLE/1/hls'.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/dataL/XILINX/Vivado/2020.2/data/ip'.
<cloudFPGA> ##  Creating IP Module: TriangleApplication ####################################
<cloudFPGA>  (in remote directory: ~/cloudFPGA/cFp_HelloThemisto/ROLE/1/ip)
<cloudFPGA>     ipName    = triangle_app
<cloudFPGA>     ipVendor  = IBM
<cloudFPGA>     ipLibrary = hls
<cloudFPGA>     ipVersion = 1.0
<cloudFPGA>     ipCfgList = 
WARNING: [Vivado 12-818] No files matched '*'
<cloudFPGA> <D1> Done with 'my_clean_ip' (RC=0).
<cloudFPGA> <D1> Done with 'create_ip' (errMsg=).
WARNING: [Coretcl 2-176] No IPs found
<cloudFPGA> ERROR: ## Failed to create IP 'TriangleApplication'.
<cloudFPGA> 

<cloudFPGA> End at: 20:09:24 Sat Jan 22 2022 
<cloudFPGA> ################################################################################
<cloudFPGA> ##
<cloudFPGA> ##  DONE WITH THE CREATION OF [ 1 ] IP CORE(S) FROM THE MANAGED IP REPOSITORY 
<cloudFPGA> ##
<cloudFPGA> ##
<cloudFPGA> ERROR: ##                   Warning: Failed to generate 1 IP core(s) ! 
<cloudFPGA> ##
<cloudFPGA> ################################################################################

INFO: [Common 17-206] Exiting Vivado at Sat Jan 22 20:09:24 2022...
make[1]: *** [ip] Error 1
make[1]: Leaving directory `~/cloudFPGA/cFp_HelloThemisto/ROLE/1'
make: *** [Role2] Error 2

[zrlhle]

Needs more work, but not critical (deferred) ... closing for now