AXI interface cannot be synthesized by Vitis

[chhzh123]

The interface generated by .to cannot pass the Vitis synthesis. An example is shown below.

def test_vitis():
    qtype = hcl.UInt(1)
    A = hcl.placeholder((10,10), "A", dtype=qtype)
    def kernel(A):
        return hcl.compute((10,10), lambda x, y: A[x][y] | 1, "B", dtype=qtype)
    s = hcl.create_schedule(A, kernel)
    target = hcl.platform.aws_f1
    target.config(compile="vitis", mode="hw_exe", backend="vhls")
    s.to(A, target.xcel)
    s.to(kernel.B,target.host)
    f = hcl.build(s, target=target)
    np_A = np.random.random((10,10))
    np_B = np.zeros((10,10))
    hcl_A = hcl.asarray(np_A)
    hcl_B = hcl.asarray(np_B)
    f(hcl_A, hcl_B)

void test(ap_uint<1> A[10][10])
#pragma HLS INTERFACE m_axi port=A offset=slave bundle=gmem0
#pragma HLS INTERFACE s_axilite port=A bundle=control

ERROR: [v++ 203-801] Interface parameter bitwidth 'A.V' (heterocl-demo/s1-project/kernel.cpp:15:1)
 must be a multiple of 8 for AXI4 master port.
ERROR: [v++ 200-70] Failed building synthesis data model.
ERROR: [v++ 60-300] Failed to build kernel(ip) test, see log for details:
 heterocl-demo/s1-project/_x.hw.xilinx_u280_xdma_201920_1/kernel/test/vivado_hls.log

Another test case here.

void test(ap_uint<1> input_image[1][1][16][16])
#pragma HLS INTERFACE m_axi port=input_image offset=slave bundle=gmem0
#pragma HLS INTERFACE s_axilite port=input_image bundle=control

ERROR: [v++ 203-801] Bitwidth of (packed) data on axi master must be power of 2:
 Found 'input_image.V' (packed) has a bitwidth of 160.
ERROR: [v++ 200-70] Failed building synthesis data model.
ERROR: [v++ 60-300] Failed to build kernel(ip) test, see log for details: 
 heterocl-demo/bnn/lab5775/project/_x.hw_emu.xilinx_u280_xdma_201920_1/kernel/test/vivado_hls.log
ERROR: [v++ 60-599] Kernel compilation failed to complete
ERROR: [v++ 60-592] Failed to finish compilation

Both of them need to pad the input data to meet the constraints given by Vitis.

[hecmay]

Issued fixed. HCL will check the interface before generating code for Vitis. Test cases added here: https://github.com/cornell-zhang/heterocl/blob/heteroflow/tests/issues/test_issue_261.py