Vivado HLS takes too long to synthesize the HeteroCL design

Question

Vivado HLS takes too long to synthesize the HeteroCL design

Opened this issue 4 years ago · 1 comments

HeteroCL generates flat designs that do not have function calls. Even the same modules (stages) will be repeated in the generated code for several times, which incurs large synthesis time.
As a comparison, a hand-written C HLS ResNet-20 may take 10 min to synthesize, while a HeteroCL generated ResNet-20 takes more than 1.5 hours.

Answer 1 · 2020-09-13T00:45:49.000Z

@chhzh123 have you added a test case?