dale40

Pinned Repositories

BitPlaneComp
Bit-plane compression
Language:C++4 2 00
ddr2-controller
Language:Verilog00
lab3
Language:SystemVerilog00
lab1
Language:SystemVerilog10
100kSV
Language:SystemVerilog19
AIDCLite
Language:SystemVerilog31
DRAMController
Language:SystemVerilog12
rtl-actions
Language:Tcl3 3 30
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Language:Python48 15 10039
Bit-Plane-Compression
Language:Verilog11

dale40's Repositories

dale40/BitPlaneComp
Bit-plane compression
Language:C++4 2 00
dale40/ddr2-controller
Language:Verilog00
dale40/lab3
Language:SystemVerilog00