Pinned Repositories
axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
axi_node
bender
A dependency management tool for hardware projects.
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Cores-SweRV
SweRV EH1 core
Cores-SweRV-EL2
SweRV EL2 Core
Cores-SweRVolf
FuseSoC-based SoC for SweRV EH1
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
edalize
An abstraction library for interfacing EDA tools
dawidzim's Repositories
dawidzim/edalize
An abstraction library for interfacing EDA tools
dawidzim/axi
AXI4 and AXI4-Lite synthesizable modules and verification infrastructure
dawidzim/axi_node
dawidzim/bender
A dependency management tool for hardware projects.
dawidzim/core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
dawidzim/Cores-SweRV
SweRV EH1 core
dawidzim/Cores-SweRV-EL2
SweRV EL2 Core
dawidzim/Cores-SweRVolf
FuseSoC-based SoC for SweRV EH1
dawidzim/cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
dawidzim/cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
dawidzim/fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
dawidzim/fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
dawidzim/ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
dawidzim/opentitan
OpenTitan: Open source silicon root of trust
dawidzim/riscv-dv
SV/UVM based instruction generator for RISC-V processor verification