Create the SDK Project

[toniomtb]

Dear mr. @dgschwend,
I'm interested to test your CNN on Xilinx UltraScale+. I've generated the fpga_top IP with Vivado HLS and used it to create an hardware platform for the ZCU102 part with Vivado.
I've never used Vivado SDK so i'm right now stucked and don't know how to proceed, can you give me some advice on how to create a executable with SDK that uses the fpga_top IP? Another question, for creating the executable can i use the same .cpp files of the test bench used in Vivado HLS to execute the same test but on the board?

Thanks in advance,
Antonio.

[dgschwend]

Hi Antonio Thanks for your interest. I haven‘t tried the project with UltraScale+ myself, looking forward to hearing about your results and experiences. I would recommend you start with some tutorials and guides for Vivado SDK / Xilinx SDK (e.g. google for „vivado sdk tutorial zynq“ and take a look at the videos and PDFs). You can export the hardware definitions from Vivado Design Suite using something like File>Export>Export Hardware or Project > Export Hardware Design to SDK. You should then be able to use the same C code which was used as the testbench in Vivado HLS to run the tests on FPGA. Regards David

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Am 17.01.2018 um 11:34 schrieb Antonio Marra ***@***.***>: Dear mr. @dgschwend, I'm interested to test your CNN on Xilinx UltraScale+. I've generated the fpga_top IP with Vivado HLS and used it to create an hardware platform for the ZCU102 part with Vivado. I've never used Vivado SDK so i'm right now stucked and don't know how to proceed, can you give me some advice on how to create a executable with SDK that uses the fpga_top IP? Another question, for creating the executable can i use the same .cpp files of the test bench used in Vivado HLS to execute the same test but on the board? Thanks in advance, Antonio. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub, or mute the thread.