Another ZYNQ board

[JackChenofNCP]

Hi, David. I am interested in you zynqnet. It's really a great work. Thanks for sharing. I learnt a lot from you report and code. So I am trying to test you CNN on my own ZedBoard these days and have met 2 problems.

1. I have imported you HLS code files into my HLS project correctly according to one of your previous reply to @wswsamao and synthesised successfully. But I met these errors while running C simulation as showed in this picture:

I am not quite familiar with HLS. Could you please help me figuring out why this occured? Thank you. And this is a screenshot of my project for you to check if I made some primary mistake as a new learner of HLS.

2. I checked the "Evaluation and Results" in your report and found that the resource ultilization exceeds the range of my ZedBoard. You used 996 BLOCK RAMs for you CNN design but I only get 500 on my board.
   So it seems I have to make some simplification to your zynqnet in order to test it on my board. And I know of course that will damage the performance of your CNN but I really want to make it work on my board. So could you give me some advice on how to shrinking down the size of your zynqnet without causing too much damage to the performance? Thanks. Looking forward to your reply.