Can dhara be used for NOR flash?
FreddieChopin opened this issue · 1 comments
This is a question, not an issue report (;
Can dhara be used with no issues on a typical serial NOR flash? I have no experience with NAND and just basic knowledge about this technology, but I understand that the differences would basically boil down to these:
- NOR has no ECC, as it generally doesn't need it, it also has no OOB, if some cells become damaged, then the chip is most likely dead anyway,
- serial NOR is much smaller (like a few MB usually),
- the size of erasable block is smaller (usually 4 kB - 64 kB),
- the size of programmable block is smaller (256/512 B).
I understand that first point makes it impossible to check for read errors and to mark pages as "bad" - both of these are probably not needed, assuming that dhara checks for data consistency (for example to recover after power failure) in some other way. For such a memory I would therefore implement dhara_nand_is_bad()
to always return "block is perfectly OK" with no checks, and dhara_nand_mark_bad()
to be a no-op (or even an assertion, as this should never be called anyway).
Is this a good or a bad idea to use dhara on such chip? Or maybe it just needs some special handling somewhere?
Side question, assuming that I could use it. In most (all?) NOR flashes you can program individual bytes of a page in separate operations with no issues. I guess that setting log2_page_size
to 1
is not such a great idea, but how low can this be set and is there a "sweet spot"? Could I set it just to the typical 256/512 bytes, or maybe a better option would be to set it higher or lower?
Thanks in advance!