Review my register file
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I just finished the first version of dyt_register_file, it was fun but I have no idea if it's correct. I based it off of this file: https://github.com/lowRISC/ibex/blob/master/rtl/ibex_register_file_ff.sv
also some of these
https://courses.cs.washington.edu/courses/cse370/10sp/pdfs/lectures/regfile.txt
http://www.cs.cornell.edu/courses/cs3410/2019sp/schedule/slides/06-cpu-pre-bw.pdf
I was a bit confused with what sytax is specific to system verilog.
Just give it a look and let me know how it is. Also if you want me to text you instead of opening issues, let me know
Looking at the logic it seems like it's okay. There are a few issues, however, that arise from using SV constructs that I don't believe icarus verilog will support. I may be wrong though. I'm also not sure on using individual write enable signals. I feel like it would be overkill. I think you could get away with using a single write enable signal and just setting the address. i.e. 1 WEN & 1 w_addr. Yash do you have any comments on that?
I've tried making a testbench and running files, but I'm having a lot of issues right now with iccarus verilog. I think I need to take some more time and do setup work. I think having a single write enable and address might be simpler. I'm still trying to figure out what system verilog concepts would work in iverilog.
Cool, thanks for the feedback guys. I'll try to make edits next time I get a chance. I also just need to do some playing around in iverilog to get a hang of it
I created an interface for the register file and removed the individual WEN signals. Other than that the logic was sound.