elhep/AFCZ

Issues

• Resistor with designator '1'

  #108 opened 4 years ago
  0

• EN_USB_JTAG should be connected directly to pin 13 od J6

  #107 opened 4 years ago
  1

• USB JTAG TRSTn is disconnected in two places

  #106 opened 4 years ago
  0

• Should MMC TRSTn be connected to other TRSTn?

  #105 opened 4 years ago
  3

• FPGA TMS pullup is unnececary

  #104 opened 4 years ago
  0

• TCK is pulled up and down

  #103 opened 4 years ago
  2

• Si5324 schematic is included in repo but not in project

  #102 opened 4 years ago
  1

• DNP some capacitors in default variant

  #101 opened 4 years ago
  0

• Could we unify BC847 and BSS138?

  #100 opened 4 years ago
  2

• Add RC filter on INA inputs

  #99 opened 4 years ago
  0

• Increase C989 to 100nF

  #98 opened 4 years ago
  0

• Swap AMC current measurment labels

  #97 opened 4 years ago
  0

• EN_RTM_MP is pulled down twice

  #96 opened 4 years ago
  1

• AMC_En is pulled up twice

  #95 opened 4 years ago
  1

• Power monitor (INA3221) warning/error signals are not connected to MMC

  #94 opened 4 years ago
  0

• HW_ID is the same as in v1.0

  #93 opened 4 years ago
  0

• Move R61 up

  #92 opened 4 years ago
  0

• Change FPGA_RESETn net name to PS_SRST

  #91 opened 4 years ago
  0

• JTAG CONFIG presence signals are not connected to actual presence signals

  #90 opened 4 years ago
  1

• Unify GPIO expanders

  #89 opened 4 years ago
  2

• FPGA_MUX_Reset can be driven from two sources

  #88 opened 4 years ago
  2

• P3V3MP is shorted to ground

  #87 opened 4 years ago
  0

• Remove unused signals from ETH1 MII harness

  #86 opened 4 years ago
  0

• Move IC76 to MMC schematics

  #85 opened 4 years ago
  0

• Break out MMC-PL SPI to a separate harness

  #84 opened 4 years ago
  0

• Move SW2 to LP1776 MMC 2 schematic

  #83 opened 4 years ago
  0

• Change R468 (MGTRREF) to 0,5% or better

  #82 opened 4 years ago
  0

• DDR4 x72 TEN signal is pulled down twice

  #81 opened 4 years ago
  0

• QSPI1/2 CLK is pulled low

  #80 opened 4 years ago
  0

• [CERN] Invalid FGPA_CLOCKS.FPGA_CLK3 connection

  #79 opened 4 years ago
  0

• PS has disabled access to flash when P3V3MP is low

  #78 opened 4 years ago
  6

• Add pullup/down resistor on FPGA_SPI_FLASH_UPD.EN_FLASH_UPDATE line

  #77 opened 4 years ago
  1

• MDIO connections

  #76 opened 4 years ago
  0

• ETH1_MII.MII1_MDIO is pulled up three times

  #75 opened 4 years ago
  0

• TXS0102DCUR has integrated pullup resistors

  #74 opened 4 years ago
  0

• Move DDR4 x16 ALERT_B pullup to SDRAM schematics

  #73 opened 4 years ago
  0

• TEN signal should be pulled down on DDR4 x16

  #72 opened 4 years ago
  0

• RESET_B should be pulled down on DDR4x16

  #71 opened 4 years ago
  0

• Change R449 and R450 from 1k to ~200 Ohm

  #70 opened 4 years ago
  0

• SDRAM VTT PGOOD is pulled up in two places

  #69 opened 4 years ago
  0

• Change DDR CK termination capacitor to 10nF

  #68 opened 4 years ago
  0

• DQS signals should have _P and _N suffixes to be recognised as differential pairs

  #67 opened 4 years ago
  0

• FMC1 has a dangling power port P3V3MP.2

  #66 opened 4 years ago
  0

• Do FMC1 and FMC2 differ?

  #65 opened 4 years ago
  1

• USB_VBUS should have 120uF

  #64 opened 4 years ago
  0

• Shouldn't IC56 be an AND gate?

  #63 opened 4 years ago
  3

• DTR and RTS lines on MMC console

  #62 opened 4 years ago
  3

• Clean up IC20 connections

  #61 opened 4 years ago
  0

• IC20 doesn't have a decoupling cap

  #60 opened 4 years ago
  0

• Unify SN74AVC2T245RSWR and TXB0304RUTR

  #59 opened 4 years ago
  4