emu-russia/breaks

Core HDL

ogamespec opened this issue · 0 comments

ogamespec commented

Create a 6502 model on Verilog and do functional tests.

What's left:

  • alu.v
  • brk.v
  • bus_control.v
  • data_bus.v
  • flags.v
  • pc.v
  • pc_control.v
  • Run in Icarus without hung
  • debug wires
    • Clocks (PHI0, PHI1, PHI2)
    • Timing (Txx)
    • Completion (ENDS, ENDX, TRESxx)
    • Flags
    • IR, PD, Implied, TwoCycle
    • PC (PCH/PCL), PCS (PCHS/PCLS)
    • Regs (A, X, Y, S)
    • AB, DIR, DOR
    • Internal buses: SB, DB, ADL, ADH
    • Bops
    • ALU Intermediate regs (AI, BI, ADD)
    • ALU Carry In, ACR, AVR
    • Ready, WRMode
  • gtkw template