emu-russia/breaks

Corrections for PPU topology and signals

ogamespec opened this issue · 1 comments

ogamespec commented

We need to mass correct the comments from ttlworks.

  • inserted transparent latches into reg.$2003 DB0..7 input, transparent when /WR=0, because of the PAL delayed write.
  • FSM HOR.: looks like F/NT is low_active, renamed it to #F/NT.
  • FSM HOR.: PAR/O is generated by an inverting super buffer, the FET switching PAR/O to GND is not marked as such in your transistor level picture.

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ogamespec commented 

CLPB=0 disables the background.
CLPO=1 disables the sprites.

To me, it feels like polarity of one signal could be wrong, please check...```