Physical address for PCIe devices
NickeZ opened this issue · 14 comments
NickeZ commented
Hi,
I can't seem to figure out how to get the physical address for my mTCA EVR receiver through mrfioc2. I would suspect that I need to modify both devlib2 and mrfioc2. Is this correct? Could you please give me some directions to where I should add this functionality?
I'm also not really sure why the physical slot is 2-1 and not 2.
$ lspci -s 7:0 -vvvxx
07:00.0 Signal processing controller: Xilinx Corporation Device 7011
Subsystem: Device 1a3e:132c
Physical Slot: 2-1
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
Latency: 0, Cache Line Size: 64 bytes
Interrupt: pin A routed to IRQ 19
Region 0: Memory at c0700000 (32-bit, non-prefetchable) [size=256K]
Capabilities: [40] Power Management version 3
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 NoSoftRst+ PME-Enable- DSel=0 DScale=0 PME-
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Address: 0000000000000000 Data: 0000
Capabilities: [60] Express (v2) Endpoint, MSI 00
DevCap: MaxPayload 256 bytes, PhantFunc 1, Latency L0s <64ns, L1 <1us
ExtTag+ AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+
MaxPayload 256 bytes, MaxReadReq 512 bytes
DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s, Exit Latency L0s unlimited, L1 unlimited
ClockPM- Surprise- LLActRep- BwNot-
LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta: Speed 2.5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
Compliance De-emphasis: -6dB
LnkSta2: Current De-emphasis Level: -3.5dB, EqualizationComplete-, EqualizationPhase1-
EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
Capabilities: [100 v1] Device Serial Number 00-00-00-00-00-00-00-00
Kernel driver in use: mrf-pci
00: ee 10 11 70 07 00 10 00 00 00 80 11 10 00 00 00
10: 00 00 70 c0 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 3e 1a 2c 13
30: 00 00 00 00 40 00 00 00 00 00 00 00 0a 01 00 00
NickeZ commented
Interesting, seems like this was implemented like 15 hours ago...
mdavidsaver commented
Ah, good timing then :) Can you test? If you run the following commands, what do you see?
lspci -t
ls /sys/bus/pci/slots
cat /sys/bus/pci/slots/*/addressI need to modify both devlib2 and mrfioc2
mrfioc2 has not been updated yet.
I'm also not really sure why the physical slot is 2-1 and not 2
I'm not certain either. I'd be interested to know what lspci -t shows.
NickeZ commented
sure happy to test
[root@icsb-mtcacpu-ct028 ~]# lspci -t
-[0000:00]-+-00.0
+-01.0-[01-10]--+-00.0-[02-10]--+-01.0-[03-0f]----00.0-[04-0f]--+-00.0-[05]--
| | | +-01.0-[06]--
| | | +-02.0-[07]----00.0
| | | +-08.0-[08]----00.0
| | | +-09.0-[09]--
| | | +-0a.0-[0a]--
| | | +-0b.0-[0b]--
| | | +-10.0-[0c]--
| | | +-11.0-[0d]--
| | | +-12.0-[0e]--
| | | \-13.0-[0f]--
| | \-02.0-[10]--
| +-00.1
| +-00.2
| +-00.3
| \-00.4
+-01.1-[11]--
+-02.0
+-14.0
+-16.0
+-19.0
+-1a.0
+-1b.0
+-1c.0-[12]--+-00.0
| \-00.1
+-1c.4-[13]----00.0
+-1d.0
+-1f.0
+-1f.2
+-1f.3
\-1f.5
[root@icsb-mtcacpu-ct028 ~]# ls /sys/bus/pci/slots
1 10 11 12 2 2-1 3 4 5 6 7 8 9
[root@icsb-mtcacpu-ct028 ~]# cat /sys/bus/pci/slots/*/address
0000:0c:00
0000:0a:00
0000:0b:00
0000:03:00
0000:07:00
0000:10:00
0000:06:00
0000:05:00
0000:08:00
0000:09:00
0000:0f:00
0000:0e:00
0000:0d:00
NickeZ commented
This is a mTCA crate with one CT CPU, one mTCA EVR and one SIS8300 in it.
[root@icsb-mtcacpu-ct028 ~]# lspci
00:00.0 Host bridge: Intel Corporation 3rd Gen Core processor DRAM Controller (rev 09)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09)
00:01.1 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09)
00:02.0 VGA compatible controller: Intel Corporation 3rd Gen Core processor Graphics Controller (rev 09)
00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller (rev 04)
00:16.0 Communication controller: Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 (rev 04)
00:19.0 Ethernet controller: Intel Corporation 82579LM Gigabit Network Connection (rev 04)
00:1a.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 (rev 04)
00:1b.0 Audio device: Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller (rev 04)
00:1c.0 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 1 (rev c4)
00:1c.4 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 5 (rev c4)
00:1d.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 (rev 04)
00:1f.0 ISA bridge: Intel Corporation QM77 Express Chipset LPC Controller (rev 04)
00:1f.2 IDE interface: Intel Corporation 7 Series Chipset Family 4-port SATA Controller [IDE mode] (rev 04)
00:1f.3 SMBus: Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller (rev 04)
00:1f.5 IDE interface: Intel Corporation 7 Series Chipset Family 2-port SATA Controller [IDE mode] (rev 04)
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA (rev ca)
01:00.1 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
01:00.2 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
01:00.3 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
01:00.4 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA (rev ca)
02:02.0 PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA (rev ca)
03:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:01.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:02.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:08.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:09.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:0a.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:0b.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:10.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:11.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:12.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
04:13.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca)
07:00.0 Signal processing controller: Xilinx Corporation Device 7011
08:00.0 Communication controller: Research Centre Juelich Device 0018
12:00.0 Ethernet controller: Intel Corporation 82580 Gigabit Backplane Connection (rev 01)
12:00.1 Ethernet controller: Intel Corporation 82580 Gigabit Backplane Connection (rev 01)
13:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network Connection
mdavidsaver commented
For reference. The same for a FRIB crate.
root@mtcacpu03:~# lspci -t
-[0000:00]-+-00.0
+-01.0-[01-0d]----00.0-[02-0d]--+-00.0-[03]--
| +-01.0-[04]--
| +-02.0-[05]--
| +-03.0-[06]----00.0
| +-08.0-[07]----00.0
| +-09.0-[08]--
| +-0a.0-[09]--
| +-10.0-[0a]--
| +-11.0-[0b]--
| +-12.0-[0c]--
| \-13.0-[0d]--
+-02.0
+-14.0
+-16.0
+-16.3
+-19.0
+-1a.0
+-1c.0-[0e]----00.0
+-1d.0
+-1f.0
+-1f.2
\-1f.3
root@mtcacpu03:~# ls /sys/bus/pci/slots
1 10 11 2 3 4 5 6 7 8 9
root@mtcacpu03:~# cat /sys/bus/pci/slots/*/address
0000:03:00
0000:08:00
0000:0d:00
0000:0b:00
0000:06:00
0000:04:00
0000:07:00
0000:09:00
0000:0c:00
0000:0a:00
0000:05:00mdavidsaver commented
I'm also not really sure why the physical slot is 2-1 and not 2
I'm not certain either. I'd be interested to know what lspci -t shows.
It looks like Linux adds "-#" to disambiguate when duplicate slot numbers are found. In Linux 3.16 see make_slot_name() in driver/pci/slot.c.
This breaks an assumption I was unwittingly making yesterday...
What does lspci -vv| egrep '^0|Slot #' show for you?
# lspci -vv| egrep '^0|Slot #'
00:00.0 Host bridge: Intel Corporation 3rd Gen Core processor DRAM Controller (rev 09)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09) (prog-if 00 [Normal decode])
Slot #9, PowerLimit 75.000W; Interlock- NoCompl+
00:02.0 VGA compatible controller: Intel Corporation 3rd Gen Core processor Graphics Controller (rev 09) (prog-if 00 [VGA controller])
00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller (rev 04) (prog-if 30 [XHCI])
00:16.0 Communication controller: Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 (rev 04)
00:16.3 Serial controller: Intel Corporation 7 Series/C210 Series Chipset Family KT Controller (rev 04) (prog-if 02 [16550])
00:19.0 Ethernet controller: Intel Corporation 82579LM Gigabit Network Connection (rev 04)
00:1a.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 (rev 04) (prog-if 20 [EHCI])
00:1c.0 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 1 (rev c4) (prog-if 00 [Normal decode])
Slot #1, PowerLimit 10.000W; Interlock- NoCompl+
00:1d.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 (rev 04) (prog-if 20 [EHCI])
00:1f.0 ISA bridge: Intel Corporation QM77 Express Chipset LPC Controller (rev 04)
00:1f.2 SATA controller: Intel Corporation 7 Series Chipset Family 6-port SATA Controller [AHCI mode] (rev 04) (prog-if 01 [AHCI 1.0])
00:1f.3 SMBus: Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller (rev 04)
01:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
02:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #10, PowerLimit 25.000W; Interlock- NoCompl-
02:01.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #4, PowerLimit 25.000W; Interlock- NoCompl-
02:02.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #9, PowerLimit 25.000W; Interlock- NoCompl-
02:03.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #3, PowerLimit 25.000W; Interlock- NoCompl-
02:08.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #5, PowerLimit 25.000W; Interlock- NoCompl-
02:09.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #11, PowerLimit 25.000W; Interlock- NoCompl-
02:0a.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #6, PowerLimit 25.000W; Interlock- NoCompl-
02:10.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #8, PowerLimit 25.000W; Interlock- NoCompl-
02:11.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #2, PowerLimit 25.000W; Interlock- NoCompl-
02:12.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #7, PowerLimit 25.000W; Interlock- NoCompl-
02:13.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #1, PowerLimit 25.000W; Interlock- NoCompl-
06:00.0 Signal processing controller: Xilinx Corporation Default PCIe endpoint ID
07:00.0 Bridge: Xilinx Corporation Device fdbe
0e:00.0 Ethernet controller: Intel Corporation I350 Gigabit Backplane Connection (rev 01)mdavidsaver commented
I've pushed up a change to deal with non-numeric slot numbers (sigh...). Can you build the latest and run:
./testApp/O.linux-x86_64/lspcix 2 0 slot=2
./testApp/O.linux-x86_64/lspcix 2 0 slot=2-1The first should match 7:0.0, the second should give No Match.
NickeZ commented
Would this mean that i should be reporting a bug to the mtca hub
manufacturer? Or how can there be two slots with the same number?
I will run the tests for you on Monday when i have access to the crate
again.
Den 15 juli 2016 4:11 em skrev "mdavidsaver" notifications@github.com:
I've pushed up a change to deal with non-numeric slot numbers (sigh...).
Can you build the latest and run:./testApp/O.linux-x86_64/lspcix 2 0 slot=2
./testApp/O.linux-x86_64/lspcix 2 0 slot=2-1The first should match 7:0.0, the second should give No Match.
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You are receiving this because you modified the open/close state.
Reply to this email directly, view it on GitHub
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mdavidsaver commented
Would this mean that i should be reporting a bug to the mtca hub manufacturer?
Couldn't hurt to ask.
Or how can there be two slots with the same number?
I'm not sure how slot numbers are given out. Even in my crate there are two bridges advertising "Slot #1" and "Slot #9". I think that one pair is from the MCH and one from the CPU. However I don't see slot "1-1" or "9-1".
I will run the tests for you on Monday when i have access to the crate again.
Ok, hope you enjoy your weekend.
mdavidsaver commented
Or how can there be two slots with the same number?
As I think about it, this situation is unavoidable for a multi-function device. So devlib2 has to handle it.
NickeZ commented
I ran your commands:
[root@icsb-mtcacpu-ct028 ~]# lspci -vv| egrep '^0|Slot #'
00:00.0 Host bridge: Intel Corporation 3rd Gen Core processor DRAM Controller (rev 09)
00:01.0 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09) (prog-if 00 [Normal decode])
Slot #1, PowerLimit 75.000W; Interlock- NoCompl+
00:01.1 PCI bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor PCI Express Root Port (rev 09) (prog-if 00 [Normal decode])
Slot #2, PowerLimit 75.000W; Interlock- NoCompl+
00:02.0 VGA compatible controller: Intel Corporation 3rd Gen Core processor Graphics Controller (rev 09) (prog-if 00 [VGA controller])
00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller (rev 04) (prog-if 30 [XHCI])
00:16.0 Communication controller: Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 (rev 04)
00:19.0 Ethernet controller: Intel Corporation 82579LM Gigabit Network Connection (rev 04)
00:1a.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 (rev 04) (prog-if 20 [EHCI])
00:1b.0 Audio device: Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller (rev 04)
00:1c.0 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 1 (rev c4) (prog-if 00 [Normal decode])
Slot #0, PowerLimit 25.000W; Interlock- NoCompl+
00:1c.4 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 5 (rev c4) (prog-if 00 [Normal decode])
Slot #4, PowerLimit 10.000W; Interlock- NoCompl+
00:1d.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 (rev 04) (prog-if 20 [EHCI])
00:1f.0 ISA bridge: Intel Corporation QM77 Express Chipset LPC Controller (rev 04)
00:1f.2 IDE interface: Intel Corporation 7 Series Chipset Family 4-port SATA Controller [IDE mode] (rev 04) (prog-if 8f [Master SecP SecO PriP PriO])
00:1f.3 SMBus: Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller (rev 04)
00:1f.5 IDE interface: Intel Corporation 7 Series Chipset Family 2-port SATA Controller [IDE mode] (rev 04) (prog-if 85 [Master SecO PriO])
01:00.0 PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA (rev ca) (prog-if 00 [Normal decode])
01:00.1 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
01:00.2 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
01:00.3 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
01:00.4 System peripheral: PLX Technology, Inc. Device 87d0 (rev ca)
02:01.0 PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA (rev ca) (prog-if 00 [Normal decode])
Slot #1, PowerLimit 25.000W; Interlock- NoCompl-
02:02.0 PCI bridge: PLX Technology, Inc. PEX 8717 16-lane, 8-Port PCI Express Gen 3 (8.0 GT/s) Switch with DMA (rev ca) (prog-if 00 [Normal decode])
Slot #2, PowerLimit 25.000W; Interlock- NoCompl-
03:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
04:00.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #4, PowerLimit 25.000W; Interlock- NoCompl-
04:01.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #3, PowerLimit 25.000W; Interlock- NoCompl-
04:02.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #2, PowerLimit 25.000W; Interlock- NoCompl-
04:08.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #5, PowerLimit 25.000W; Interlock- NoCompl-
04:09.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #6, PowerLimit 25.000W; Interlock- NoCompl-
04:0a.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #11, PowerLimit 25.000W; Interlock- NoCompl-
04:0b.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #12, PowerLimit 25.000W; Interlock- NoCompl-
04:10.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #10, PowerLimit 25.000W; Interlock- NoCompl-
04:11.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #9, PowerLimit 25.000W; Interlock- NoCompl-
04:12.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #8, PowerLimit 25.000W; Interlock- NoCompl-
04:13.0 PCI bridge: PLX Technology, Inc. Device 8748 (rev ca) (prog-if 00 [Normal decode])
Slot #7, PowerLimit 25.000W; Interlock- NoCompl-
07:00.0 Signal processing controller: Xilinx Corporation Device 7011
[root@icsb-mtcacpu-ct028 ~]# requireExec devlib2,niklasclaesson lspcix 2 0 slot=2
No match
[root@icsb-mtcacpu-ct028 ~]# requireExec devlib2,niklasclaesson lspcix 2 0 slot=2-1
PCI 0000:07:00.0 IRQ 10
vendor:device 10ee:7011 rev 00
subved:subdev 1a3e:132c
class 118000 generic signal processing controller
slot: 2-1
BAR 0 32-bit MMIO 256 kB
mdavidsaver commented
The first should match 7:0.0, the second should give No Match.
So, my statement was exactly backwards :P You should see "slot=2-1" match 7:00.0 because /sys/bus/pci/slots/2-1/address contains 0000:07:00.
Does this new code add the feature you need? Are there any additional tests you can think of? Otherwise I'll do a release with this and the fix for #1.
And thank you for this fortuitous timed ticket. That slot numbers aren't always numbers was a good fact to discover before the new API was released.
NickeZ commented
Does this new code add the feature you need?
Yes I think so. Will you also update mrfioc2 to enable finding the card by using slot number? Otherwise I will probably try to look into it.
Are there any additional tests you can think of?
No can't really think of any more special cases. It was also pure accident that I noticed this one.
mdavidsaver commented
devlib2 2.8 is now released