Implementation for FPGA, branch on 4th column NOT work
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conv.zip
When implementing a convolution with a 16x1 input and a 3x1 filter for an FPGA with an interleaved bus, a bug occurs if branching happens in the 4th column, where the system fails to execute the jump. This issue may be related to several warnings issued by Vivado, indicating suboptimal connections that could potentially cause hold violation problems.
To reproduce the bug, I upload the folder conv: this folder should replace the one presented inside sw/applications/kernel_test/kernels/
To address this bug, I have so far altered the assembly instructions by relocating the branch instruction from the 4th column to the 3rd. This adjustment necessitated minor modifications to the C code as well.
conv-worked.zip