ferrilab/bitvec

Ordering bug comparing Vec & Slice

superfell opened this issue · 0 comments

In the following test, the 2 asserts where there's a bitvec on the left and a slice on the right will fail.

    #[test]
    fn test_bitvec_order() {
        let k = bitvec![0, 1, 0, 1];
        let r = bitvec![1, 0, 0, 0];
        let k_slice = &k[..];
        let r_slice = &r[..];
        assert!(r > k);
        assert!(k < r);
        assert!(r_slice > k_slice);
        assert!(k_slice < r_slice);
        assert!(r_slice > k);
        assert!(k < r_slice);
        assert!(k_slice < r);
        assert!(r > k_slice);
    }

I believe this is due to the PartialOrd implementation at https://github.com/ferrilab/bitvec/blob/main/src/vec/traits.rs#L201 which swaps the order of self & other around.