fischermoseley/manta

Issues

• Not enough bytes received during Logic Analyzer capture

  #18 opened 9 months ago by KennethWilke
  16

• help with 'Only got 0 out of 7 bytes'

  #20 opened 7 months ago by pm100
  2

• Reference examples in documentation site

  #22 opened 8 months ago by fischermoseley
  0

• Port examples to the Nexys Video

  #21 opened 8 months ago by fischermoseley
  0

• Yosys-compatible verilog

  #14 opened 8 months ago by TheZoq2
  2

• Switch from Scapy to builtin Python sockets library

  #11 opened 10 months ago by fischermoseley
  0

• Refactor block_memory addressing scheme to not use modulo operator

  #7 opened 10 months ago by fischermoseley
  0

• Re-add some Logic Analyzer core features

  #9 opened 10 months ago by fischermoseley
  0

• Add method for dumping logic analyzer contents to Python

  #5 opened 10 months ago by fischermoseley
  0

• Convert block_memory address/data/write enable arrays to unpacked

  #6 opened 10 months ago by fischermoseley
  0

• Re-add some IO core features

  #8 opened a year ago by fischermoseley
  0

• Fix Ethernet packet format

  #10 opened a year ago by fischermoseley
  0