Verilator simulation errors out with "Latch inferred" warning

[tomverbeure]

With a recent version of verilator, I get the following:

tom@zen:~/tools/jtag_vpi/sim/run$ make sim_verilator
make -f Makefile.verilator -C ../bin sim
make[1]: Entering directory '/home/tom/tools/jtag_vpi/sim/bin'
verilator --trace -cc -Wno-UNOPTFLAT -Wno-COMBDLY  -Wno-WIDTH  -Wno-BLKSEQ -Wno-UNUSED -Wno-CASEINCOMPLETE -Wno-PINMISSING   -Wno-PINCONNECTEMPTY -Wno-ASSIGNDLY -I../../bench/verilog/include  ../../bench/verilog/jtag_soc.v ../../bench/verilog/jtag_tap/jtag_tap.v  ../../bench/verilog/adv_debugsys/*.v ../../bench/verilog/ram/ram_wb_b3.v
%Warning-LATCH: ../../bench/verilog/ram/ram_wb_b3.v:71:4: Latch inferred for signal 'burst_adr_counter' (not all control paths of combinational always assign a value)
                                                        : ... In instance jtag_soc.ram
                                                        : ... Suggest use of always_latch for intentional latches
   71 |    always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
      |    ^~~~~~
                ... For warning description see https://verilator.org/warn/LATCH?v=4.212
                ... Use "/* verilator lint_off LATCH */" and lint_on around source to disable this message.
%Error: Exiting due to 1 warning(s)

I can make it simulate by adding the 2 lines at the bottom:

   // Burst address generation logic
   always @(wb_ack_o or wb_b3_trans or wb_b3_trans_start
            or wb_bte_i_r or wb_cti_i_r or wb_adr_i or adr)
     if (wb_b3_trans_start)
       // Kick off burst_adr_counter, this assumes 4-byte words when getting
       // address off incoming Wishbone bus address! 
       // So if dw is no longer 4 bytes, change this!
       burst_adr_counter = wb_adr_i[mem_adr_width-1:2];
     else if ((wb_cti_i_r == 3'b010) & wb_ack_o & wb_b3_trans) // Incrementing burst
       case(wb_bte_i_r)
         2'b00 : burst_adr_counter      = adr + 1; // Linear burst
         2'b01 : burst_adr_counter[1:0] = adr[1:0] + 1; // 4-beat wrap burst
         2'b10 : burst_adr_counter[2:0] = adr[2:0] + 1; // 8-beat wrap burst
         2'b11 : burst_adr_counter[3:0] = adr[3:0] + 1; // 16-beat wrap burst
       endcase
     else                // <<<<<<<<<<<<<<<<<
       burst_adr_counter = adr;  // <<<<<<<<<<<<<<

[fjullien]

Thank you. This should be fixed in 57fdbea.