forensicgarlic

forensicgarlic's Stars

• cr1901/sentinel

  Another size-optimized RISC-V CPU for your consideration.

  Language:Python462

• cocotb/cocotb-bus

  Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  Language:Python5539

• Xilinx/HLS_packet_processing

  Language:C++4421

• osresearch/fpga-class

  Intro to FPGA class projects

  Language:Verilog5

• pwsafe/pwsafe

  Password Safe - popular secure and convenient password manager

  Language:C++725148

• lccidocker/osstools

  Docker image with Open Source EDA tools

  4

• tinyfpga/TinyFPGA-B-Series

  Open source design files for the TinyFPGA B-Series boards.

  Language:Verilog19035

• ZipCPU/wbuart32

  A simple, basic, formally verified UART controller

  Language:Verilog27647

• cocotb/cocotb

  cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  Language:Python1.8k504

• Obijuan/open-fpga-verilog-tutorial

  Learn how to design digital systems and synthesize them into an FPGA using only opensource tools

  Language:Verilog768195

• FPGAwars/apio

  :seedling: Open source ecosystem for open FPGA boards

  Language:Verilog793136

• laanwj/yosys-ice-experiments

  Experiments for iCEstick evaluation board with iCE40HX-1k FPGA - using open source toolchain

  Language:Verilog13

• CodeReclaimers/myhdl-experiments

  Language:Python31

• YosysHQ/icestorm

  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)

  Language:Python983224

• cfelton/myhdl_exercises

  MyHDL exercises.

  Language:Jupyter Notebook91