foss-for-synopsys-dwc-arc-processors/linux

Is there any sample code to illustrate how to use PAE+MMU for the usage of 40 bits address?

wimowa opened this issue · 2 comments

Dear all,

After check the databook, I understand Hs48 can support 40 bits address, but how to implement it in real case? Does current Linux Arc CPU sw have support PAE 40 bits? and where?

Thanks.

ARC Linux supports PAE since v4.6 (2016).
The following high level aspects are needed to supporting PAE.

  1. Defining physical address to be 64-bit
    This is implemented via CONFIG_PHYS_ADDR_T_64BIT (and selected automatically if CONFIG_ARC_HAS_PAE40)

  2. Enabling MMU driver to program 64-bit TLB entries
    This is implemented via CONFIG_HIGHMEM and CONFIG_ARC_HAS_PAE40
    TLB bits are implemented in arch/arc/mm/{tlb.c, tlbex.S}

  3. Specifying PAE memory region in platform's Device Tree: e.g. arch/arc/boot/dts/hsdk.dts

        memory@80000000 {
                #address-cells = <2>;
                #size-cells = <2>;
                device_type = "memory";
-               reg = <0x0 0x80000000 0x0 0x40000000>;  /* 1 GB lowmem */
+               reg = <0x0 0x80000000 0x0 0x40000000    /* 1 GB lowmem */
+                      0x1 0x00000000 0x0 0x40000000>;  /* 1 GB highmem */
        };
  1. Managing memory beyond 4GB (in an otherwise 32-bit system)
    This is mostly done in generic code, with arch/arc/mm/init.c having code to populate the PAE regions.

Vladimir recently posted a few PAE related fixes - which landed in v5.13-rc2 kernel upstream.
2021-04-27 1d5e464 ARC: mm: Use max_high_pfn as a HIGHMEM zone border
2021-04-27 c5f756d ARC: mm: PAE: use 40-bit physical page mask

Thank you very much.
I really really appreciate all these information.