Improve documentation of GCC options for ARCv3

[abrodkin]

Currently we only have a table (https://foss-for-synopsys-dwc-arc-processors.github.io/experimental-documentation/2023.09/toolchain/target-options/#arcv3-toolchain) with mapping of -msimd, -mll64, -m128 to various -mcpu options.
But looking at real output of the GCC (at least the one from ARC 2023.09 release) we may see way more options:

$ module load arc_gnu/2023.09-elf-arc64
$ arc64-elf-gcc --target-help
The following options are target specific:
  -m128                       Enable wide data transfer support.
  -matomic=                   Enable atomic instructions: {0, 1, 2, 3}.
  -mbbit                      Generate BBITx instructions during combiner step.
  -mbitscan                   Enable NORM, NORMH, FFS, FLS, NORML, FFSL, and FLSL bitscan instructions.
  -mbrcc                      Generate BRcc instructions during combiner step.
  -mcmodel=                   Specify the code model.
  -mcode-density              Enable code-density instructions.
  -mcpu=                      -mcpu=CPU Generate code for specific ARCv3 CPU variant.
  -mdiv-rem                   Enable DIV-REM instructions.
  -mexperimental              Experimental option, to be removed.
  -mfpmov                     Reduce pressure on GPRs by using FPRs for memory operations like memcpy.
  -mfpu=                      Specify hardware FP model used.
  -mll64                      Enable double load/store instructions for arc64:32.
  -msimd                      Enable integer SIMD instructions.
  -munaligned-access          Enable unaligned accesse for packed data.
  -mvolatile-di               Enable uncached access for volatile memories.
  -mwide                      Enable wide floating point SIMD support.

  The code model option names for -mcmodel:
    large medium small

Assembler options
=================

Use "-Wa,OPTION" to pass "OPTION" to the assembler.

ARC64-specific assembler options:
  -mcpu=<cpu name>        assemble for CPU <cpu name>,one of:
                          hs6x, hs5x, hs68, hs58

And while above is already helpful, would be really nice to add the following information:

• How above option relate to various -mcpu templates, i.e. what's enabled and what is not. Something in the style of https://foss-for-synopsys-dwc-arc-processors.github.io/experimental-documentation/2023.09/toolchain/target-options/#target-options will do.
• There's no explanation of -mfpu options, which could be either none, fpus (single precision FPU ) or fpud (single & double precision FPU).
• How all the options above could be mapped to ARChitect options, i.e. how can we get GCC settings most suitable to our particular design? That last bullet once resolved will help to generate GCC settings for ARCv3 by ARChitect tools via tcfgen tool and finally users will be able to use their .tcf files for compiler configuration... even if not directly feeding their .tcf to the GCC (we may do it with help of https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/blob/arc-releases/extras/arc-tcf-gcc) but at least extracting ful set of options from .tcf and passing them directly to the GCC.