fvutils/pyvsc

Enh: Support Default bin (How to write "default" in vsc.coverpoint ?)

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Discussed in #185

Originally posted by jiyong00 August 8, 2023
Does anyone know how to write "default" as vsc.coverpoint in systemverilog style coverpoint as follows?

    zero_delay : coverpoint cov_delay {
      bins ZERO = {1};
      bins MORE = default;  
    }
```</div>