gatecat

FPGA tool dev • kbitycat • blåhaj fan • she/they • 🏳️‍🌈🏳️‍⚧️🐱🦈🦈🦈

nya~!DE

Pinned Repositories

BreadboardSim
Circuit Simulator with Breadboard UI
Language:C#86 5 630
CSI2Rx
Open Source 4k CSI-2 Rx core for Xilinx FPGAs
Language:VHDL374 39 6103
hrt
Hot Reconfiguration Technology demo
Language:Verilog38 3 00
meowality
Language:Python15 4 01
nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
Language:C++206 19 3341
prjoxide
Documenting Lattice's 28nm FPGA parts
Language:Python143 18 1915
TrellisBoard
Ultimate ECP5 development board
Language:ANTLR101 11 910
nextpnr
nextpnr portable FPGA place and route tool
Language:C++1.3k 72 425242
prjtrellis
Documenting the Lattice ECP5 bit-stream format.
Language:Python398 35 7086
yosys
Yosys Open SYnthesis Suite
Language:C++3.4k 138 1.7k872

gatecat's Repositories

gatecat/nextpnr-xilinx
Experimental flows using nextpnr for Xilinx devices
Language:C++206 19 3341
gatecat/prjoxide
Documenting Lattice's 28nm FPGA parts
Language:Python143 18 1915
gatecat/meowality
Language:Python15 4 01
gatecat/nextpnr-xilinx-meta
Metadata for the nextpnr-xilinx xc7 flow
9 2 13
gatecat/openvtx
Emulator for VT168 etc
Language:C++9 2 02
gatecat/emu293
emu293 SPG293 emulator and associated tooling
Language:C++7 2 1
gatecat/mistral-test
Language:Verilog6 3 1
gatecat/fabulous-mpw2-bringup
Language:Verilog3 1 02
gatecat/fabulous-tapeout-automation
Language:Python3
gatecat/one_hot_fpga_gf180
FPGA with a custom SRAM+mux bitcell for onehot routing
Language:Verilog3 1 0
gatecat/litex
Build your hardware, easily!
2
gatecat/prjoxide-db
prjoxide database
2 5 04
gatecat/coriolis
Coriolis VLSI EDA Tool (LIP6)
Language:C++1 0 0
gatecat/fabulous_mpd
Example digital project for the Efabless Caravel "openframe" harness
Language:Verilog1 0 0
gatecat/fabulous_mpw0gf
fabulous efpga tapeout on gf180
Language:Verilog1 1 0
gatecat/litex-boards
LiteX boards files
Language:Python1 0 0
gatecat/mister_nes_gfmpw1
Language:Verilog1 1 0
gatecat/nextpnr
nextpnr portable FPGA place and route tool
1
gatecat/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow
1
gatecat/caravel_board
Language:C0 0
gatecat/FABulous
Fabric generator and CAD tools
gatecat/mapnik
Mapnik is an open source toolkit for developing mapping applications
Language:C++0 0
gatecat/one-hot-fpga-gf180-3x3
3x3 variant to be less demanding on precheck
Language:Verilog
gatecat/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
gatecat/openstreetmap-carto
A general-purpose OpenStreetMap mapnik style, in CartoCSS
Language:CartoCSS0 0
gatecat/picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
gatecat/pythondata-cpu-cv32e40p
Python module containing system_verilog files for cv32e40p cpu (for use with LiteX).
gatecat/riscv-dbg
RISC-V Debug Support for our PULP RISC-V Cores
Language:SystemVerilog0 0
gatecat/scratching-post
Language:Python1 0
gatecat/sky130_klayout_pdk
Skywaters 130nm Klayout PDK