cmd/internal/obj/riscv: support Zihintntl assembly on riscv64

[newborn22]

Zihintntl Extension Overview

The zihintntl extension introduces non-temporal locality hints through the NTL.* instruction family. These instructions advise the memory subsystem that the data accessed by subsequent load or store operations exhibits no temporal locality and thus should not be cached at specified levels. As hint instructions, their execution by the processor is optional.

Instruction Details:

NTL.P1

Description: Indicates that the target memory access lacks temporal locality within the capacity of the innermost level of private cache in the memory hierarchy.
Assembly Implementation: ADD x0, x0, x2
Machine Code Encoding:

         31      25 24   20 19   15 14  12 11    11    7 6      0
        ┌─────────┬───────┬───────┬──────┬──────┬────────┐
        │ 0000000 │ 00010 │ 00000 │ 000  │ 00000│ 0110011│
        └─────────┴───────┴───────┴──────┴──────┴────────┘

NTL.PALL

Description: Indicates that the target memory access lacks temporal locality within the capacity of any level of private cache.
Assembly Implementation: ADD x0, x0, x3
Machine Code Encoding:

         31      25 24   20 19   15 14  12 11    7 6      0
        ┌─────────┬───────┬───────┬──────┬──────┬────────┐
        │ 0000000 │ 00011 │ 00000 │ 000  │ 00000│ 0110011│
        └─────────┴───────┴───────┴──────┴──────┴────────┘

NTL.S1

Description: Indicates that the target memory access lacks temporal locality within the capacity of the innermost level of shared cache.
Assembly Implementation: ADD x0, x0, x4
Machine Code Encoding:

         31      25 24   20 19   15 14  12 11    7 6      0
        ┌─────────┬───────┬───────┬──────┬──────┬────────┐
        │ 0000000 │ 00100 │ 00000 │ 000  │ 00000│ 0110011│
        └─────────┴───────┴───────┴──────┴──────┴────────┘

NTL.ALL

Description: Indicates that the target memory access lacks temporal locality within the capacity of any level of cache (both private and shared).
Assembly ImplementationAssembly Implementation: ADD x0, x0, x5
Machine Code Encoding:

         31      25 24   20 19   15 14  12 11    7 6      0
        ┌─────────┬───────┬───────┬──────┬──────┬────────┐
        │ 0000000 │ 00101 │ 00000 │ 000  │ 00000│ 0110011│
        └─────────┴───────┴───────┴──────┴──────┴────────┘

[gopherbot]

Change https://go.dev/cl/717940 mentions this issue: cmd/internal/obj/riscv: support Zihintntl assembly on RISCV64

[gabyhelp]

Related Issues

• cmd/internal/obj/riscv: support zawrs assembly on riscv64 #76179

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[prattmic]

cc @golang/riscv64