google/CFU-Playground

Open OCD shows DEPRECATED. Unable to get output.

mamuneeb opened this issue · 2 comments

mamuneeb commented

Hii @tcal-x
I was following the setup guide for build.
After running the below command :
make prog TARGET=digilent_arty USE_SYMBIFLOW=1 EXTRA_LITEX_ARGS="--variant=a7-100" EXTRA_LITEX_ARGS="--sys-clk-freq 75000000"
I am getting this :

make[2]: Entering directory '/home/mamuneebcfu/CFU-Playground/proj/proj_template'
/home/mamuneebcfu/CFU-Playground/scripts/pyrun /home/mamuneebcfu/CFU-Playground/proj/proj_template/cfu_gen.py
make -C /home/mamuneebcfu/CFU-Playground/soc -f /home/mamuneebcfu/CFU-Playground/soc/common_soc.mk prog
make[3]: Entering directory '/home/mamuneebcfu/CFU-Playground/soc'
Timing check performed only for Vivado.
Loading bitstream onto board
MAKEFLAGS=-j8 /home/mamuneebcfu/CFU-Playground/scripts/pyrun ./common_soc.py --output-dir build/digilent_arty.proj_template --csr-json build/digilent_arty.proj_template/csr.json --cpu-cfu /home/mamuneebcfu/CFU-Playground/proj/proj_template/cfu.v --uart-baudrate 1843200 --target digilent_arty --sys-clk-freq 75000000 --toolchain symbiflow --no-compile-software --load
make_soc: cpu_variant is full+cfu
Variant "full+cfu" already known.
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:S7PLL:Creating ClkOut0 sys of 75.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 eth of 25.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut2 sys4x of 300.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut3 sys4x_dqs of 300.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut4 idelay of 200.00MHz (+-10000.00ppm).
INFO:SoC: __ _ __ _ __
INFO:SoC: / / () /___ | |//
INFO:SoC: / /__/ / __/ -)> <
INFO:SoC: ///_/_//|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2022-09-22 05:10:57)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a35ticsg324-1L.
INFO:SoC:System clock: 75.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 1.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:leds CSR allocated at Location 3.
INFO:SoCCSRHandler:sdram CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCCSRHandler:uart CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)

  • cpu_bus0
  • cpu_bus1
    Bus Slaves: (4)
  • rom
  • sram
  • main_ram
  • csr
    INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
    CSR Locations: (7)
  • ctrl : 0
  • ddrphy : 1
  • identifier_mem : 2
  • leds : 3
  • sdram : 4
  • timer0 : 5
  • uart : 6
    INFO:SoC:IRQ Handler (up to 32 Locations).
    IRQ Locations: (2)
  • uart : 0
  • timer0 : 1
    INFO:SoC:--------------------------------------------------------------------------------
    INFO:S7PLL:Config:
    divclk_divide : 1
    clkout1_freq : 25.00MHz
    clkout1_divide: 48
    clkout1_phase : 0.00掳
    clkout4_freq : 200.00MHz
    clkout4_divide: 6
    clkout4_phase : 0.00掳
    clkout0_freq : 75.00MHz
    clkout0_divide: 16
    clkout0_phase : 0.00掳
    clkout2_freq : 300.00MHz
    clkout2_divide: 4
    clkout2_phase : 0.00掳
    clkout3_freq : 300.00MHz
    clkout3_divide: 4
    clkout3_phase : 90.00掳
    vco : 1200.00MHz
    clkfbout_mult : 12
    sources is causing rebuild for synth
    eblif is causing rebuild for fasm
    sdc is causing rebuild for pack
    net is causing rebuild for fasm
    io_place is causing rebuild for place_constraints
    place_constraints is causing rebuild for place
    place is causing rebuild for fasm
    route is causing rebuild for fasm
    fasm_extra is causing rebuild for fasm
    fasm is causing rebuild for bitstream

Project status:
[R] bitstream: bitstream -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.bit
[O] build_dir: /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware
[R] eblif: synth -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.eblif
[R] fasm: fasm -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.fasm
[R] fasm_extra: synth -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty_fasm_extra.fasm
[R] io_place: ioplace -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.ioplace
[R] net: pack -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.net
[X] pcf: MISSING
[R] place: place -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.place
[R] place_constraints: place_constraints -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.preplace
[R] route: route -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.route
[R] sdc: synth -> /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.sdc
[N] sources: ['/home/mamuneebcfu/CFU-Playground/proj/proj_template/cfu.v', '/home/mamuneebcfu/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v', '/home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.v']
[O] xdc: /home/mamuneebcfu/CFU-Playground/soc/build/digilent_arty.proj_template/gateware/digilent_arty.xdc

Open On-Chip Debugger 0.12.0-rc1+dev-00001-gb89cf71e2-dirty (2022-09-19-08:07)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid'
DEPRECATED! use 'ftdi channel' not 'ftdi_channel'
DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init'
Info : auto-selecting first available session transport "jtag". To override use 'transport select '.
DEPRECATED! use 'adapter speed' not 'adapter_khz'

fpga_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 25000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x13631093 (mfg: 0x049 (Xilinx), part: 0x3631, ver: 0x1)
make[3]: Leaving directory '/home/mamuneebcfu/CFU-Playground/soc'
make[2]: Leaving directory '/home/mamuneebcfu/CFU-Playground/proj/proj_template'

According to the setup guide, i must see the chasing LED pattern but its not showing.

I am using Arty A7-100T.

Is there any issues with the clock frequency.

Please help me with this.
Thank you.

tcal-x commented

Hello @mamuneeb ,

I think the DEPRECATED! message is typical and can be ignored. Yes, that is unfortunate. In fact this may be a good reason for us to switch to using https://github.com/trabucayre/openFPGALoader, another open source project.

But, if you don't see the LED pattern, then something is wrong. I don't have an Arty board handy where I'm at now, so I'll try to reproduce it later.

OH, I see your problem:

INFO:SoC:FPGA device : xc7a35ticsg324-1L.

There can only be one EXTRA_LITEX_ARGS definition (only the last one is used). So you need to replace:

EXTRA_LITEX_ARGS="--variant=a7-100" EXTRA_LITEX_ARGS="--sys-clk-freq 75000000"

with

EXTRA_LITEX_ARGS="--variant=a7-100  --sys-clk-freq 75000000"
mamuneeb commented

The issue is resolved.
Thank you