google/CFU-Playground

make prog issue

ggangliu opened this issue · 2 comments

ggangliu commented

My board is arty_100, I met this problem when I execute "make prog". May I get some tips or help, thanks. The log show as below.

"(cfu-symbiflow) ggang@ubuntu:~/CFU-Playground/proj/proj_arty7_100$ make prog
make[2]: Entering directory '/home/ggang/CFU-Playground/proj/proj_arty7_100'
/home/ggang/CFU-Playground/scripts/pyrun /home/ggang/CFU-Playground/proj/proj_arty7_100/cfu_gen.py
make -C /home/ggang/CFU-Playground/soc -f /home/ggang/CFU-Playground/soc/common_soc.mk prog
make[3]: Entering directory '/home/ggang/CFU-Playground/soc'
Timing check performed only for Vivado.
Loading bitstream onto board
MAKEFLAGS=-j8 /home/ggang/CFU-Playground/scripts/pyrun ./common_soc.py --output-dir build/digilent_arty.proj_arty7_100 --csr-json build/digilent_arty.proj_arty7_100/csr.json --cpu-cfu /home/ggang/CFU-Playground/proj/proj_arty7_100/cfu.v --uart-baudrate 1843200 --target digilent_arty --toolchain symbiflow --no-compile-software --load
INFO:Workflow:Setting sys_clk_freq to 75MHz.
make_soc: cpu_variant is full+cfu
Variant "full+cfu" already known.
INFO:S7PLL:Creating S7PLL, speedgrade -1.
INFO:S7PLL:Registering Single Ended ClkIn of 100.00MHz.
INFO:S7PLL:Creating ClkOut0 sys of 75.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut1 eth of 25.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut2 sys4x of 300.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut3 sys4x_dqs of 300.00MHz (+-10000.00ppm).
INFO:S7PLL:Creating ClkOut4 idelay of 200.00MHz (+-10000.00ppm).
INFO:SoC: __ _ __ _ __
INFO:SoC: / / () /___ | |//
INFO:SoC: / /__/ / __/ -)> <
INFO:SoC: ///_/_//|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-03-30 06:30:39)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xc7a100tcsg324-1.
INFO:SoC:System clock: 75.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoCBusHandler:main_ram Region added at Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:main_ram added as Bus Slave.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 4).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:ddrphy CSR allocated at Location 1.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 2.
INFO:SoCCSRHandler:leds CSR allocated at Location 3.
INFO:SoCCSRHandler:sdram CSR allocated at Location 4.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 5.
INFO:SoCCSRHandler:uart CSR allocated at Location 6.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0 : Origin: 0x80000000, Size: 0x80000000, Mode: RW, Cached: False Linker: False
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00020000, Mode: R, Cached: True Linker: False
sram : Origin: 0x10000000, Size: 0x00002000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0xf0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
Bus Masters: (2)

  • cpu_bus0
  • cpu_bus1
    Bus Slaves: (4)
  • rom
  • sram
  • main_ram
  • csr
    INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
    CSR Locations: (7)
  • ctrl : 0
  • ddrphy : 1
  • identifier_mem : 2
  • leds : 3
  • sdram : 4
  • timer0 : 5
  • uart : 6
    INFO:SoC:IRQ Handler (up to 32 Locations).
    IRQ Locations: (2)
  • uart : 0
  • timer0 : 1
    INFO:SoC:--------------------------------------------------------------------------------
    INFO:S7PLL:Config:
    divclk_divide : 1
    clkout1_freq : 25.00MHz
    clkout1_divide: 48
    clkout1_phase : 0.00°
    clkout4_freq : 200.00MHz
    clkout4_divide: 6
    clkout4_phase : 0.00°
    clkout0_freq : 75.00MHz
    clkout0_divide: 16
    clkout0_phase : 0.00°
    clkout2_freq : 300.00MHz
    clkout2_divide: 4
    clkout2_phase : 0.00°
    clkout3_freq : 300.00MHz
    clkout3_divide: 4
    clkout3_phase : 90.00°
    vco : 1200.00MHz
    clkfbout_mult : 12
    sources is causing rebuild for synth
    eblif is causing rebuild for fasm
    sdc is causing rebuild for pack
    net is causing rebuild for fasm
    io_place is causing rebuild for place_constraints
    place_constraints is causing rebuild for place
    place is causing rebuild for fasm
    route is causing rebuild for fasm
    fasm_extra is causing rebuild for fasm
    fasm is causing rebuild for bitstream

Project status:
[R] bitstream: bitstream -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.bit
[O] build_dir: /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware
[R] eblif: synth -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.eblif
[R] fasm: fasm -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.fasm
[R] fasm_extra: synth -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty_fasm_extra.fasm
[R] io_place: ioplace -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.ioplace
[R] net: pack -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.net
[X] pcf: MISSING
[R] place: place -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.place
[R] place_constraints: place_constraints -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.preplace
[R] route: route -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.route
[R] sdc: synth -> /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.sdc
[N] sources: ['/home/ggang/CFU-Playground/proj/proj_arty7_100/cfu.v', '/home/ggang/CFU-Playground/third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v', '/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.v']
[O] xdc: /home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.xdc

config: prog/openocd_xc7_ft2232.cfg script: init; pld load 0 {/home/ggang/CFU-Playground/soc/build/digilent_arty.proj_arty7_100/gateware/digilent_arty.bit}; exit
Open On-Chip Debugger 0.12.0-rc2+dev-00019-g9d925776b-dirty (2022-11-15-23:15)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
DEPRECATED! use 'adapter driver' not 'interface'
DEPRECATED! use 'ftdi vid_pid' not 'ftdi_vid_pid'
DEPRECATED! use 'ftdi channel' not 'ftdi_channel'
DEPRECATED! use 'ftdi layout_init' not 'ftdi_layout_init'
Info : auto-selecting first available session transport "jtag". To override use 'transport select '.
DEPRECATED! use 'adapter speed' not 'adapter_khz'
fpga_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi tdo_sample_edge falling"
Info : clock speed 25000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x13631093 (mfg: 0x049 (Xilinx), part: 0x3631, ver: 0x1)
make[3]: Leaving directory '/home/ggang/CFU-Playground/soc'
make[2]: Leaving directory '/home/ggang/CFU-Playground/proj/proj_arty7_100'
"

ggangliu commented

I'm not sure if it's because which components version is not correct. list here also.

(cfu-symbiflow) ggang@ubuntu:~/CFU-Playground/proj/proj_arty7_100$ conda list | grep litex-hub
binutils-riscv32-elf 2.34 20220706_160221 litex-hub
dfu-util 0.11_7_g919aea9 20220706_155948 litex-hub
flterm 2.4_31_g8898c78 20220706_155948 litex-hub
gcc-riscv32-elf-newlib 10.1.0 20220706_160221 litex-hub
gcc-riscv32-elf-nostdc 10.1.0 20220706_160221 litex-hub
gperftools 2.15_93_gb81d639 20240223_100318 litex-hub
iceprog 0.0_719_g792cef0 20220706_155948 litex-hub
icestorm 0.0_719_g792cef0 20240223_100318 litex-hub
isl 0.21 20210924_145025 litex-hub
libftdi 1.3 20220706_155948 litex-hub
libhidapi 0.12.0_23_g2b70208 20220706_155948 litex-hub
libusb 1.0.20 20220706_155948 litex-hub
nextpnr-ecp5 0.7_11_g05ed9308 20240223_100318_py37 litex-hub
nextpnr-ice40 0.7_11_g05ed9308 20240223_100318_py37 litex-hub
nextpnr-nexus 0.7_11_g05ed9308 20240223_100318_py37 litex-hub
openfpgaloader 0.9.1_42_gd5190a3 20220706_155948 litex-hub
openocd 0.12.0_rc2_19_g9d925776b 20220706_155948 litex-hub
prjoxide 0.0_447_g30712ff 20240223_100318 litex-hub
prjtrellis 1.4_66_g2dab009 20240223_100318_py37 litex-hub
prjxray-db 0.0_257_g0a0adde 20240223_100318 litex-hub
prjxray-tools 0.1_3246_g5b9b5090 20240223_100318 litex-hub
surelog 1.82_61_g2c4aba06b5 20240223_100318_py37 litex-hub
symbiflow-yosys-plugins 1.20230425_62_g0ad1af2 20230606_125334 litex-hub
verilator 5.022_1_g881c6ee65 20240223_100318 litex-hub
vtr-optimized 8.0.0_6959_ga7fae8fb2 20230131_213614 litex-hub
yosys 0.33_11_g31ee566ec 20230724_080446_py37 litex-hub

ggangliu commented

I tried to fix it as warning info mentioned. Modifying the openocd_xc7_ft2232.cfg as below content, it seems worked. And my cable connection is not stable I found which also is a question sometime for some issues. But LD11 light is always flashing which means that power supply is good , but USB connection sometime don't show in host side. I am not sure why.

adapter driver ftdi
ftdi vid_pid 0x0403 0x6010
ftdi channel 0
ftdi layout_init 0x00e8 0x60eb
reset_config none

source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]
adapter speed 25000

proc fpga_program {} {
    global _CHIPNAME
    xc7_program $_CHIPNAME.tap
}