spike on ULPI D4, D7 data bus when asserting STP

[ronyrus]

This happens from time to time.
When asserting STP in the end of TX, all the data lines are supposed to be 0x00 (or 0xFF in some cases), but in steady state.
Instead, from time to time a short spike can be observed on D4 and/or D7.
The pulse is 0.8v-1.9v with the duration of ~2.5 ns

Spike on D7: (red - STP, blue - D7)

Spike on D4

Seems to be not PHY specific. I was able to reproduce it on "host" and "target" PHYs.

To reproduce I've used the 'simple_device' design from the examples.
I'm able to trigger it on D7 with a single 'get_descriptor' control transfer.
It gets the STALL response, hence the try-except in the code.

#!/usr/bin/env python3

import time
import usb1

print("sending packets ... Ctrl-C to stop")
while True:
    try:
        with usb1.USBContext() as context:
            device = context.openByVendorIDAndProductID(0x16d0, 0x0f3b)
            device.claimInterface(0)
            device.controlRead(0x80, 6, 0x0600, 0x0000, 0x000A)
    except usb1.USBErrorPipe:
        print('.', end="", flush=True)
        time.sleep(0.5)

Later on was reproduced by @zyp

[zyp]

IIRC when we discussed this on Discord, we came to the conclusion that it's caused by the ULPI IO not being registered but driven combinatorially.

The LUT input signals doesn't necessarily all have the same propagation delay, so when two or more inputs toggle in the same cycle, the LUT may briefly see a half-old half-new input state causing it to output the wrong value, causing glitches like this. (Picture an XOR gate with the inputs switching from 00 to 11; in either case the output should be 0, but if it briefly sees 01 or 10 in between you'll get a brief 1 on the output.)

This is not really indicative of a problem; as long as the PHY chip's setup and hold times are not violated, the glitch should be harmless.