hamsternz/DisplayPort_Verilog

insert_main_stream_attrbutes_four_channels.v

Opened this issue · 0 comments

line182 default: out_data[53:36] <= { in_data[53:44], in_data[44:36]};
it should be
default: out_data[53:36] <= { in_data[53:45], in_data[44:36]};

line196 default: out_data[71:54] <= { in_data[71:64], in_data[63:56] };
it should be
default: out_data[71:54] <= { in_data[71:63], in_data[62:54] };