hamsternz/DisplayPort_Verilog

dp_aux_messages.v

m0400220334 opened this issue · 4 comments

line227 ~line285

Bit 4:3 = PRE-EMPHASIS_SET,your code set Bit 5:4 = PRE-EMPHASIS_SET

Hi! Sorry about the bugs you are finding.

I don't have easy access to my test setup any more, but if you send me a pull request I'll merge them in.

Thanks

Mike

OKay I will learn how to pull request O(∩_∩)O

OKay I will learn how to pull request O(∩_∩)O

OKay I will learn how to pull request O(∩_∩)O