hamsternz/DisplayPort_Verilog

some question on my borad genesys2 and nexys video

xhyParzival opened this issue · 0 comments

hello ,
I am using it on my genesys2 board with GTX ,but I have some questions:
1.this project cannot work on my 4k displayer with the test source 3840*2160YCC_422_CH2
2.it cannot work with the tese_source_800_600_Ch4 since I have changed the "source_channel_count" from 3'b010 to 3'b100 because I want to use 4 channels
3.in Displayport Standard V1.2.PDF,I don't find some detailed examples or informations which describes the relationship between TU and symbol_clk or stream_clk,so I cannot understand the TUs' arrangement in your test sources

now I want to wirte a project which can support 4K 60fps display,if you can help me ,I would thank you very much