/Real-time-edge-detection-on-FPGA

Computer Architecture course's project Fall 2018, Innopolis University.

Primary LanguageVerilog

Real-time-edge-detection-on-FPGA

You will find the article of the project on: https://m.habr.com/post/431326/ .

Note: if you don't read Russian and have Google translate extension, switch it off because if you are using it, it will display summarize of the article.

This project is built by a team consisting of two students: Hussein Youness and Hany Hamed in first year bachelor of Computer Science in Innopolis University in Russia.

This project is part of Computer Architecture course Fall 2018 in Innopolis University.